Change in coreboot[master]: soc/intel/alderlake: Add known CPU Port IDs for GPIO communities - coreboot-gerrit

12 May 2021


      Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Deepti Deshatty, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54087 )
Change subject: soc/intel/alderlake: Add known CPU Port IDs for GPIO communities
......................................................................
Patch Set 1: Code-Review+2
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/54087
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id5fa5b10edeb3445a2d2453d9122376041577598
Gerrit-Change-Number: 54087
Gerrit-PatchSet: 1
Gerrit-Owner: Deepti Deshatty deepti.deshatty@intel.com
Gerrit-Reviewer: Furquan Shaikh furquan@google.com
Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Attention: Furquan Shaikh furquan@google.com
Gerrit-Attention: Maulik V Vaghela maulik.v.vaghela@intel.com
Gerrit-Attention: Deepti Deshatty deepti.deshatty@intel.com
Gerrit-Attention: Patrick Rudolph siro@das-labor.org
Gerrit-Comment-Date: Wed, 12 May 2021 17:00:31 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment