Change in coreboot[master]: soc/intel/common/block: Add SoC overrides for SATA initialization

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/23589

Change subject: soc/intel/common/block: Add SoC overrides for SATA initialization
......................................................................

soc/intel/common/block: Add SoC overrides for SATA initialization

SATA PCH configuration space registers bit mapping is different
for various SOCs hence common API between SPT-PCH and CNL-PCH causing
issue.

Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a
Signed-off-by: Subrata Banik 
---
A src/soc/intel/common/block/include/intelblocks/sata.h
M src/soc/intel/common/block/sata/sata.c
2 files changed, 27 insertions(+), 37 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/23589/1

diff --git a/src/soc/intel/common/block/include/intelblocks/sata.h b/src/soc/intel/common/block/include/intelblocks/sata.h
new file mode 100644
index 0000000..c726cea
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/sata.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_SATA_H
+#define SOC_INTEL_COMMON_BLOCK_SATA_H
+
+/* SoC override SATA final initialization */
+void sata_soc_final(device_t dev);
+
+#endif	/* SOC_INTEL_COMMON_BLOCK_SATA_H */
diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c
index 791510e..f6a0a44 100644
--- a/src/soc/intel/common/block/sata/sata.c
+++ b/src/soc/intel/common/block/sata/sata.c
@@ -17,52 +17,20 @@
 #include <device/pci.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
+#include <intelblocks/sata.h>
 #include <soc/pci_devs.h>

-#define SATA_ABAR_PORT_IMPLEMENTED	0x0c
-#define SATA_PCI_CFG_PORT_CTL_STS	0x92
-
-static void *get_ahci_bar(void)
+/* SoC override SATA final initialization */
+__attribute__((weak)) void sata_soc_final(device_t dev)
 {
-	uintptr_t bar;
-	device_t dev = PCH_DEV_SATA;
-
-	bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
-	return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
-}
-
-/*
- * SATA Port control and Status. By default, the SATA ports are set (by HW)
- * to the disabled state (e.g. bits[3:0] == '0') as a result of an initial
- * power on reset. When enabled by software as per SATA port mapping,
- * the ports can transition between the on, partial and slumber states
- * and can detect devices. When disabled, the port is in the off state and
- * can't detect any devices.
- */
-static void sata_final(device_t dev)
-{
-	void *ahcibar = get_ahci_bar();
-	u32 port_impl, temp;
-
-	dev = PCH_DEV_SATA;
-
-	/* Set Bus Master */
-	temp = pci_read_config32(dev, PCI_COMMAND);
-	pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER);
-
-	/* Read Ports Implemented (GHC_PI) */
-	port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED) & 0x07;
-	/* Port enable */
-	temp = pci_read_config32(dev, SATA_PCI_CFG_PORT_CTL_STS);
-	temp |= port_impl;
-	pci_write_config32(dev, SATA_PCI_CFG_PORT_CTL_STS, temp);
+	/* no-op */
 }

static struct device_operations sata_ops = {
    .read_resources		= &pci_dev_read_resources,
    .set_resources		= &pci_dev_set_resources,
    .enable_resources	= &pci_dev_enable_resources,
-	.final			= sata_final,
+	.final			= &sata_soc_final,
    .ops_pci		= &pci_dev_ops_pci,
 };