Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39706 )
Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE ......................................................................
soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE
According to the latest Tigerlake Platform FSP Integration Guide, the minimum amount of stack needed for FSP-M is 256KiB. Change DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined empirically).
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Ic9be6446c4db7f62479deab06ebeba2c7326e681 --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/39706/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 8d066f3..ee74371 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -84,11 +84,11 @@
config DCACHE_BSP_STACK_SIZE hex - default 0x30400 + default 0x40400 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB). + sum of FSP-M stack requirement (256KiB) and CB romstage stack requirement (~1KiB).
config FSP_TEMP_RAM_SIZE hex
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39706 )
Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE ......................................................................
Patch Set 1: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39706 )
Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39706/1/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/39706/1/src/soc/intel/tigerlake/Kco... PS1, Line 87: 0x40400 Is this true for JSL as well?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39706 )
Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39706/1/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/39706/1/src/soc/intel/tigerlake/Kco... PS1, Line 87: 0x40400
Is this true for JSL as well?
I have not seen the Integration Guide for JSL. Subrata, is it valid for JSL as well?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39706 )
Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE ......................................................................
Patch Set 1: -Code-Review
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39706 )
Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39706/1/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/39706/1/src/soc/intel/tigerlake/Kco... PS1, Line 87: 0x40400
I have not seen the Integration Guide for JSL. Subrata, is it valid for JSL as well?
Will get back on this. give me little time.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39706 )
Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39706/1/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/39706/1/src/soc/intel/tigerlake/Kco... PS1, Line 87: 0x40400
I have not seen the Integration Guide for JSL. […]
Looks like JSL still has lesser requirement as per FSP integration guide
config DCACHE_BSP_STACK_SIZE hex default 0x30400 if SOC_INTEL_JASPERLAKE default 0x40400 if SOC_INTEL_TIGERLAKE
can you please help to make required changes ?
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39706 )
Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39706/1/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/39706/1/src/soc/intel/tigerlake/Kco... PS1, Line 87: 0x40400
Looks like JSL still has lesser requirement as per FSP integration guide […]
Yes, JSL stack requirement is 192Kb
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39706 )
Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39706/1/src/soc/intel/tigerlake/Kco... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/39706/1/src/soc/intel/tigerlake/Kco... PS1, Line 87: 0x40400
Yes, JSL stack requirement is 192Kb
Thanks guys!
Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Nick Vaccaro, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39706
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE ......................................................................
soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE
According to the latest Tigerlake Platform FSP Integration Guide, the minimum amount of stack needed for FSP-M is 256KiB. Change DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined empirically). JSL requires 192KiB.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Ic9be6446c4db7f62479deab06ebeba2c7326e681 --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/39706/2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39706 )
Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39706 )
Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE ......................................................................
soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE
According to the latest Tigerlake Platform FSP Integration Guide, the minimum amount of stack needed for FSP-M is 256KiB. Change DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined empirically). JSL requires 192KiB.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Ic9be6446c4db7f62479deab06ebeba2c7326e681 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39706 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 4 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 8d066f3..63bd881 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -84,11 +84,13 @@
config DCACHE_BSP_STACK_SIZE hex - default 0x30400 + default 0x40400 if SOC_INTEL_TIGERLAKE + default 0x30400 if SOC_INTEL_JASPERLAKE help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB). + sum of FSP-M stack requirement (256KiB for TGL, 192KiB for JSL) and CB romstage + stack requirement (~1KiB).
config FSP_TEMP_RAM_SIZE hex
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39706 )
Change subject: soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZE ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 5/0/5 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1646 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1645 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1644 Non-emulation targets: HP_COMPAQ_8200_ELITE_SFF_PC using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1648 HP_COMPAQ_8200_ELITE_SFF_PC using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1647
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Aamir Bohra (Code Review)
-
Furquan Shaikh (Code Review)
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Patrick Georgi (Code Review)
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Subrata Banik (Code Review)
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Tim Wawrzynczak (Code Review)