Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47653 )
Change subject: soc/intel/tigerlake: Define TCSS AUX pin bias control ......................................................................
Patch Set 3: -Code-Review
(2 comments)
https://review.coreboot.org/c/coreboot/+/47653/3/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/early_tcss.h:
https://review.coreboot.org/c/coreboot/+/47653/3/src/soc/intel/tigerlake/inc... PS3, Line 106: 0x09000000
What is this value? And how was it determined?
A chipset specific constant that the FSP consumes; it looks like it will ignore values that don't have this in the upper byte
https://review.coreboot.org/c/coreboot/+/47653/3/src/soc/intel/tigerlake/inc... PS3, Line 109: (((group) & 0xff) << 16) | ((pin) & 0xff))
In my opinion, rather than doing this in all macros and expecting mainboard to know group # pin #, i […]
That's even cleaner, I like it.
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Tim Wawrzynczak (Code Review)