Change in coreboot[master]: soc/intel/common: Drop Lewis Burg PCIe Root Port IDs

[Nico Huber (Code Review)]

Hello Aaron Durbin, Subrata Banik, Arthur Heymans, Michael Niewöhner, Duncan Laurie, Furquan Shaikh,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/35983

to review the following change.

Change subject: soc/intel/common: Drop Lewis Burg PCIe Root Port IDs
......................................................................

soc/intel/common: Drop Lewis Burg PCIe Root Port IDs

We want to split this driver up for easier maintenance. There is no
place to move these IDs, though, as they were left there dead in the
water.

Change-Id: Ia5d7de68a962a96f2694f8a6212e3aeba6bebf23
Signed-off-by: Nico Huber 
---
M src/soc/intel/common/block/pcie/pcie.c
1 file changed, 0 insertions(+), 40 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/35983/1

diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index c8ca4f4..9c95124 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -114,46 +114,6 @@
    PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18,
    PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19,
    PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP1,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP2,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP3,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP4,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP5,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP6,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP7,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP8,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP9,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP10,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP11,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP12,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP13,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP14,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP15,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP16,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP17,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP18,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP19,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP20,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP1_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP2_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP3_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP4_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP5_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP6_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP7_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP8_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP9_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP10_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP11_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP12_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP13_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP14_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP15_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP16_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP17_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP18_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP19_SUPER,
-	PCI_DEVICE_ID_INTEL_LWB_PCIE_RP20_SUPER,
    PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1,
    PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2,
    PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3,

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35983 )

Change subject: soc/intel/common: Drop Lewis Burg PCIe Root Port IDs
......................................................................

Patch Set 1:

Maxim, I'm not sure why these IDs were added. There doesn't seem
to be general support for this chipset?

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35983 )

Change subject: soc/intel/common: Drop Lewis Burg PCIe Root Port IDs
......................................................................

Patch Set 1:
> > Maxim, I'm not sure why these IDs were added. There doesn't seem
> > to be general support for this chipset?
>
> Lewisburg PCIe not tested yet
> I agree with you that these IDs should not be here.
> However, if we want to separate IDs by soc type, then we will need to create a separate directory soc/intel/pch/lewisburg for Lewisburg, since several different processors (Sky/Cascade/Cooper Lake) use this PCH

Please ignore, this was just noise. I thought it could be helpful
to have individual drivers for the root-port renumbering. Turned
out that once the PCI device code picks up the DIDs, it's too late
to patch the devicetree easily.

(I think src/southbridge/intel/ would be a much better place for PCHs)

[Nico Huber (Code Review)]

Nico Huber has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35983 )

Change subject: soc/intel/common: Drop Lewis Burg PCIe Root Port IDs
......................................................................

Abandoned

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35983 )

Change subject: soc/intel/common: Drop Lewis Burg PCIe Root Port IDs
......................................................................

Patch Set 1:
> Patch Set 1:
>
> (I think src/southbridge/intel/ would be a much better place for PCHs)

Me too. Even the lowest-power Skylake chips are two dies on a single package, so not really a SoC...