[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC

[Shuo Liu (Code Review)]

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Paul Menzel, Vasiliy Khoruzhick, [e-mail].

Shuo Liu has posted comments on this change by [e-mail]. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email )

Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
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Patch Set 50:

(3 comments)

File src/soc/intel/snowridge/chip.c:

https://review.coreboot.org/c/coreboot/+/83321/comment/83b1eda8_dc7580cd?usp... :
PS15, Line 418: 	}
> Seems there is no `enable` method in the default PCI or PCIe device operations, and the `PCI_COMMAND […]

Acknowledged

File src/soc/intel/snowridge/chip.c:

https://review.coreboot.org/c/coreboot/+/83321/comment/b964d70b_fc48d0fc?usp... :
PS50, Line 417: 		if (is_dev_on_domain0(dev) && is_pch_slot(PCI_DEV2DEVFN(PCI_BDF(dev))) &&
Seems that these static PCH devices will be assigned with an ops later by the PCI probing process, right?

https://review.coreboot.org/c/coreboot/+/83321/comment/3906fa82_3d120241?usp... :
PS50, Line 418: 		    (dev->ops == NULL || dev->ops->enable == NULL)) {
What is the benefit of (dev->ops == NULL || dev->ops->enable == NULL)?, just to double confirm it is not enabled by PCI probing yet?