Patch set updated for coreboot: timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS
Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10742
-gerrit
commit df120343ef3d730b855c926d616abcae602fd06e Author: Aaron Durbin adurbin@chromium.org Date: Thu Nov 6 09:58:07 2014 -0600
timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS
Empty functions are provided when !CONFIG_COLLECT_TIMESTAMPS so stop guarding the compilation.
BUG=None BRANCH=None TEST=Built
Original-Change-Id: Ib0f23e1204e048a9b928568da02e9661f6aa0a35 Original-Signed-off-by: Aaron Durbin adurbin@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/228190 Original-Reviewed-by: Furquan Shaikh furquan@chromium.org Original-Reviewed-by: Julius Werner jwerner@chromium.org
(cherry picked from commit 9aa69fd43d77f5f7acdc9f361016c595dd16104e) Signed-off-by: Marc Jones marc.jones@se-eng.com
Change-Id: I14418c8ef3ccb57ac6fce05b422e1c21b1d38392 --- src/arch/x86/boot/acpi.c | 4 ---- src/mainboard/google/cosmos/romstage.c | 15 ++++----------- src/mainboard/google/veyron_brain/romstage.c | 11 +++-------- src/mainboard/google/veyron_danger/romstage.c | 11 +++-------- src/mainboard/google/veyron_jerry/romstage.c | 12 ++++-------- src/mainboard/google/veyron_mickey/romstage.c | 11 +++-------- src/mainboard/google/veyron_mighty/romstage.c | 11 +++-------- src/mainboard/google/veyron_minnie/romstage.c | 12 ++++-------- src/mainboard/google/veyron_pinky/romstage.c | 14 ++++++-------- src/mainboard/google/veyron_rialto/romstage.c | 11 +++-------- src/mainboard/google/veyron_romy/romstage.c | 11 +++-------- src/mainboard/google/veyron_speedy/romstage.c | 12 ++++-------- src/southbridge/intel/bd82x6x/bootblock.c | 3 +-- src/southbridge/intel/fsp_bd82x6x/bootblock.c | 3 +-- src/southbridge/intel/i82801gx/bootblock.c | 3 +-- src/southbridge/intel/lynxpoint/bootblock.c | 3 +-- 16 files changed, 44 insertions(+), 103 deletions(-)
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index cf33e40..134e437 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -34,9 +34,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/cpu.h> #include <cbfs.h> -#if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> -#endif #include <romstage_handoff.h>
/* FIXME: Kconfig doesn't support overridable defaults :-( */ @@ -1124,9 +1122,7 @@ void acpi_jump_to_wakeup(void *vector) /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size);
-#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_ACPI_WAKE_JUMP); -#endif
acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); diff --git a/src/mainboard/google/cosmos/romstage.c b/src/mainboard/google/cosmos/romstage.c index 0988bee..e5fa67e 100644 --- a/src/mainboard/google/cosmos/romstage.c +++ b/src/mainboard/google/cosmos/romstage.c @@ -37,37 +37,30 @@
void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = timestamp_get(); start_romstage_time = timestamp_get(); -#endif
console_init();
-#if CONFIG_COLLECT_TIMESTAMPS before_dram_time = timestamp_get(); -#endif + sdram_init(); -#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = timestamp_get(); -#endif + mmu_init(); mmu_config_range(0, 4096, DCACHE_OFF); dcache_mmu_enable();
cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time); timestamp_add(TS_BEFORE_INITRAM, before_dram_time); timestamp_add(TS_AFTER_INITRAM, after_dram_time); -#endif - -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif run_ramstage(); } diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c index 3ea50b6..f243235 100644 --- a/src/mainboard/google/veyron_brain/romstage.c +++ b/src/mainboard/google/veyron_brain/romstage.c @@ -79,9 +79,7 @@ static void configure_l2ctlr(void)
void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif
console_init(); configure_l2ctlr(); @@ -89,13 +87,12 @@ void main(void)
/* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -105,9 +102,7 @@ void main(void)
cbmem_initialize_empty();
-#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif
run_ramstage(); } diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c index 0328e95..e9857b8 100644 --- a/src/mainboard/google/veyron_danger/romstage.c +++ b/src/mainboard/google/veyron_danger/romstage.c @@ -80,9 +80,7 @@ static void configure_l2ctlr(void)
void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif
console_init(); configure_l2ctlr(); @@ -93,13 +91,12 @@ void main(void)
/* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -109,9 +106,7 @@ void main(void)
cbmem_initialize_empty();
-#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif
run_ramstage(); } diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c index 06eabe0..fb6e631 100644 --- a/src/mainboard/google/veyron_jerry/romstage.c +++ b/src/mainboard/google/veyron_jerry/romstage.c @@ -85,9 +85,7 @@ static void sdmmc_power_off(void)
void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif
console_init(); configure_l2ctlr(); @@ -98,13 +96,12 @@ void main(void)
/* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -114,9 +111,8 @@ void main(void)
cbmem_initialize_empty();
-#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_END_ROMSTAGE); -#endif
run_ramstage(); } diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index 3ea50b6..f243235 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -79,9 +79,7 @@ static void configure_l2ctlr(void)
void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif
console_init(); configure_l2ctlr(); @@ -89,13 +87,12 @@ void main(void)
/* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -105,9 +102,7 @@ void main(void)
cbmem_initialize_empty();
-#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif
run_ramstage(); } diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c index 06eabe0..5ccbe3e 100644 --- a/src/mainboard/google/veyron_mighty/romstage.c +++ b/src/mainboard/google/veyron_mighty/romstage.c @@ -85,9 +85,7 @@ static void sdmmc_power_off(void)
void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif
console_init(); configure_l2ctlr(); @@ -98,13 +96,12 @@ void main(void)
/* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -114,9 +111,7 @@ void main(void)
cbmem_initialize_empty();
-#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif
run_ramstage(); } diff --git a/src/mainboard/google/veyron_minnie/romstage.c b/src/mainboard/google/veyron_minnie/romstage.c index ffdfdb0..07170b9 100644 --- a/src/mainboard/google/veyron_minnie/romstage.c +++ b/src/mainboard/google/veyron_minnie/romstage.c @@ -86,9 +86,7 @@ static void sdmmc_power_off(void)
void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif
console_init(); configure_l2ctlr(); @@ -99,13 +97,13 @@ void main(void)
/* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif +
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -115,9 +113,7 @@ void main(void)
cbmem_initialize_empty();
-#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif
run_ramstage(); } diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index 5031ad9d..492c0f0 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -93,9 +93,7 @@ static void sdmmc_power_off(void)
void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif
console_init(); configure_l2ctlr(); @@ -106,13 +104,13 @@ void main(void)
/* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif +
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -122,9 +120,9 @@ void main(void)
cbmem_initialize_empty();
-#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_END_ROMSTAGE); -#endif +
run_ramstage(); } diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index ffdfdb0..9cdacc3 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -86,9 +86,7 @@ static void sdmmc_power_off(void)
void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif
console_init(); configure_l2ctlr(); @@ -99,13 +97,12 @@ void main(void)
/* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -115,9 +112,7 @@ void main(void)
cbmem_initialize_empty();
-#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif
run_ramstage(); } diff --git a/src/mainboard/google/veyron_romy/romstage.c b/src/mainboard/google/veyron_romy/romstage.c index 3ea50b6..f243235 100644 --- a/src/mainboard/google/veyron_romy/romstage.c +++ b/src/mainboard/google/veyron_romy/romstage.c @@ -79,9 +79,7 @@ static void configure_l2ctlr(void)
void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif
console_init(); configure_l2ctlr(); @@ -89,13 +87,12 @@ void main(void)
/* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -105,9 +102,7 @@ void main(void)
cbmem_initialize_empty();
-#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif
run_ramstage(); } diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c index ffdfdb0..07170b9 100644 --- a/src/mainboard/google/veyron_speedy/romstage.c +++ b/src/mainboard/google/veyron_speedy/romstage.c @@ -86,9 +86,7 @@ static void sdmmc_power_off(void)
void main(void) { -#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_START_ROMSTAGE); -#endif
console_init(); configure_l2ctlr(); @@ -99,13 +97,13 @@ void main(void)
/* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_BEFORE_INITRAM); -#endif + sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_AFTER_INITRAM); -#endif +
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -115,9 +113,7 @@ void main(void)
cbmem_initialize_empty();
-#if CONFIG_COLLECT_TIMESTAMPS timestamp_add_now(TS_END_ROMSTAGE); -#endif
run_ramstage(); } diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 4df6bb5..18532df 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -86,9 +86,8 @@ static void set_spi_speed(void)
static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c index 46aa58f..8f6ddbc 100644 --- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c +++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c @@ -87,9 +87,8 @@ static void set_spi_speed(void)
static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 64c4410..dde1ae9 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -47,9 +47,8 @@ static void enable_spi_prefetch(void)
static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + enable_spi_prefetch();
/* Enable RCBA */ diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 6727173..8c2133b 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -87,9 +87,8 @@ static void set_spi_speed(void)
static void bootblock_southbridge_init(void) { -#if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); -#endif + map_rcba(); enable_spi_prefetch(); enable_port80_on_lpc();
-
Patrick Georgi