Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32832
Change subject: cpu/intel: Deduplicate set_var_mtrr ......................................................................
cpu/intel: Deduplicate set_var_mtrr
Multiple static copies of set_var_mtrr have found their way into the codebase. These definitions conflict with the global declaration in src/include/cpu/x86/mtrr.h, which causes a compilation error in Clang. This removes all the duplicates. Some of the parameter types are slightly different (int vs unsigned int), but for the arguments where the duplicates are called it doesn't matter.
Signed-off-by: Jacob Garber jgarber1@ualberta.ca Change-Id: I9971433c4c6a02c532d17acedc37f9119599ca52 --- M src/cpu/intel/fsp_model_406dx/bootblock.c M src/cpu/intel/model_2065x/bootblock.c M src/cpu/intel/model_206ax/bootblock.c M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/fsp_baytrail/bootblock/bootblock.c 7 files changed, 0 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/32832/1
diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index 14cfad9..0abe9e8 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -44,18 +44,6 @@ } }
-static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - static void enable_rom_caching(void) { msr_t msr; diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c index 19dbda8..39e9f04 100644 --- a/src/cpu/intel/model_2065x/bootblock.c +++ b/src/cpu/intel/model_2065x/bootblock.c @@ -30,21 +30,6 @@ #error "CPU must be paired with Intel Ibex Peak southbridge" #endif
-static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) - -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - static void enable_rom_caching(void) { msr_t msr; diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 9dcbe37..16e7bd5 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -32,21 +32,6 @@ #error "CPU must be paired with Intel BD82X6X or C216 southbridge" #endif
-static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) - -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - static void enable_rom_caching(void) { msr_t msr; diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index b2cdf9d..6275d77 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -20,17 +20,6 @@ #include <soc/iosf.h> #include <cpu/intel/microcode/microcode.c>
-static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) -{ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - static void enable_rom_caching(void) { msr_t msr; diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 457b8b8..62073aa 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -21,17 +21,6 @@ #include <soc/iosf.h> #include <cpu/intel/microcode/microcode.c>
-static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) -{ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - static void enable_rom_caching(void) { msr_t msr; diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index 2f1ac51..c79e2b8 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -23,19 +23,6 @@ #include <soc/rcba.h> #include <soc/msr.h>
-static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - static void enable_rom_caching(void) { msr_t msr; diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c index 5351a01..689fe35 100644 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c @@ -45,17 +45,6 @@ } }
-static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) -{ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - /* * Enable Prefetching and Caching. */
Hello Patrick Rudolph, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32832
to look at the new patch set (#2).
Change subject: cpu/intel: Deduplicate set_var_mtrr ......................................................................
cpu/intel: Deduplicate set_var_mtrr
Multiple static copies of set_var_mtrr have found their way into the codebase. These definitions conflict with the global declaration in src/include/cpu/x86/mtrr.h, which causes a compilation error in Clang. This removes all the duplicates. Some of the parameter types are slightly different (int vs unsigned int), but for the arguments where the duplicates are called it doesn't matter.
Signed-off-by: Jacob Garber jgarber1@ualberta.ca Change-Id: I9971433c4c6a02c532d17acedc37f9119599ca52 --- M src/cpu/intel/fsp_model_406dx/bootblock.c M src/cpu/intel/model_2065x/bootblock.c M src/cpu/intel/model_206ax/bootblock.c M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/fsp_baytrail/bootblock/bootblock.c 6 files changed, 0 insertions(+), 75 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/32832/2
Jacob Garber has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32832 )
Change subject: cpu/intel: Deduplicate set_var_mtrr ......................................................................
Abandoned
Oops, these are actually needed for romcc, but clang doesn't understand that. Will reanalyze later.
-
Jacob Garber (Code Review)