Attention is currently required from: Duncan Laurie, Kyösti Mälkki. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52723 )
Change subject: drivers/i2c/designware: Use safe defaults for SCL parameters ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1: I gave this patch a shot on mc_apl6. No constraints provided in devicetree so that default values take precedence. The computed results of the timings are:
dw_i2c: SoC 400/3000 ns Bus: 400/1000000 ns dw_i2c: period 334 rise 0 fall 0 tlow 174 thigh 80 spk 7 dw_i2c: hcnt = 106 lcnt = 213 sda hold = 40
This results in the following measured timing on SCL: period=2,58 us (=>387,6 kHz) t_low=1,58 us t_high=1 us (both t_high and t_low includes rise and fall times) t_hold=304 ns
This is way better than it was before and there is still the possibility to tune the timing on demand in the devicetree.