Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39980 )

Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
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Patch Set 3:

I tried to find out more about the PSI3/4 states. Some facts:

- "optional for server" in IMVP7 (doc#397113) simply means there are VRs for the server segment which don't support PS3 or PS4
- PS4 is only available on SoCs supporting C10
- Intel doc#334661-006 says PS4 is "shut the VR nearly completely off"
- Intel doc#334661-006 says that C-States should be limited to C9 when the SoC supports C10 but the platform (well, I guess they mean the whole machine but basicly the VR itself) does not support PS4
- There are VRs where the DS says "compliant with IMVP8 PS4", e.g. MP2949A
- PS3 means only one phase is on in dynamic mode
- PS4 means all PWM outputs are tristated / all phases are disabled. The VR is still enabled/alive to be able to respond with nearly no delay
- The PS4 command MUST be acknowledged by the VR according to some Intel doc I forgot to note the id for :/

Long story short: if we have the datasheet for the VR of the machine, we can simply check if it supports PSI3, PSI4, both, or none. If we don't have a datasheet, we have a problem.

I could not find out, yet, what would happen when the SoC tries to request PSI3/4 but the VR does not acknowlege it. In case some error flag gets set, we could simply test it by letting the machine go to C10 and check that flag.