Change in coreboot[master]: soc/skylake: lockdown: lock ABASE

[Michael Niewöhner (Code Review)]

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35452 )

Change subject: soc/skylake: lockdown: lock ABASE
......................................................................

soc/skylake: lockdown: lock ABASE

Lock ABASE just like apollolake, cannonlake and icelake

Change-Id: Ib5412a269fd6b039342b9328eb2ed0e458f1ab9f
Signed-off-by: Michael Niewöhner 
---
M src/soc/intel/skylake/lockdown.c
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/35452/1

diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
index 89221cb..f41548b 100644
--- a/src/soc/intel/skylake/lockdown.c
+++ b/src/soc/intel/skylake/lockdown.c
@@ -28,6 +28,18 @@
    }
 }

+static void pmc_lock_abase(void)
+{
+	uint8_t *pmcbase;
+	uint32_t reg32;
+
+	pmcbase = pmc_mmio_regs();
+
+	reg32 = read32(pmcbase + GEN_PMCON_B);
+	reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
+	write32(pmcbase + GEN_PMCON_B, reg32);
+}
+
 static void pmc_lock_global_reset(void)
 {
    /* Disable global reset, just in case */
@@ -47,6 +59,8 @@
    pmsyncreg |= PMSYNC_LOCK;
    write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);

+	/* Lock down ABASE and sleep stretching policy */
+	pmc_lock_abase();
    /* Lock global reset */
    pmc_lock_global_reset();
 }

[Michael Niewöhner (Code Review)]

Michael Niewöhner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35452 )

Change subject: soc/skylake: lockdown: lock ABASE
......................................................................

Abandoned

fsp does this already.... see 21201