Change in coreboot[master]: soc/mediatek/mt8192: Do dramc software impedance calibration
Hello Duan huayang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44704
to review the following change.
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 184 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index e82f182..bf819ec 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -16,7 +16,7 @@ verstage-y += ../common/uart.c
romstage-y += ../common/cbmem.c -romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_utility.c +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c new file mode 100644 index 0000000..04ff5d7 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <timer.h> + +static const u8 imp_vref_sel[ODT_MAX][IMP_DRV_MAX] = { + /* DRVP DRVN ODTP ODTN */ + [ODT_OFF] = {0x37, 0x33, 0x00, 0x37}, + [ODT_ON] = {0x3a, 0x33, 0x00, 0x3a}, +}; + +static void dramc_imp_cal_vref_sel(dram_odt_state odt, imp_drv_type drv_type) +{ + u8 vref_tmp = 0; + vref_tmp = imp_vref_sel[odt][drv_type]; + + switch (drv_type) { + case DRVP: + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP, vref_tmp); + break; + case DRVN: + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN, vref_tmp); + break; + case ODTN: + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN, vref_tmp); + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } +} + +static u32 dramc_sw_imp_cal_result(imp_drv_type drv_type) +{ + u32 drive = 0, cal_res = 0; + u32 change = (drv_type == DRVP) ? 1: 0; + + const char *drv_str = NULL; + switch (drv_type) { + case DRVP: + drv_str = "DRVP"; + break; + case DRVN: + drv_str = "DRVN"; + break; + case ODTP: + drv_str = "ODTP"; + break; + case ODTN: + drv_str = "ODTN"; + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } + + for (drive = 0; drive < 32; drive++) { + if (drv_type == DRVP) + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVP, drive); + else if (drv_type == DRVN || drv_type == ODTN) + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVN, drive); + + udelay(1); + cal_res = READ32_BITFIELD(&ch[0].phy_nao.misc_phy_rgs_cmd, + MISC_PHY_RGS_CMD_RGS_RIMPCALOUT); + dramc_dbg("OCD %s=%d ,CALOUT=%d\n", drv_str, drive, cal_res); + + if (cal_res == change) { + dramc_info("%s calibration OK! result=%d\n", drv_str, drive); + break; + } + } + + if (drive == 32) { + drive = 31; + dramc_err("OCD %s calibration FAIL! %s=%d\n", drv_str, drv_str, drive); + } + + return drive; +} + +void dramc_sw_impedance_cal(dram_odt_state odt, struct dram_impedance *imp) +{ + u8 chn = 0, i_chn, enp, enn; + u32 bc_bak, impcal_bak, cal_res = 0; + u32 drvp_result = 0xff, odtn_result = 0xff, drvn_result = 0xff; + + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (i_chn = 0; i_chn < CHANNEL_MAX; i_chn++) { + SET32_BITFIELDS(&ch[i_chn].phy_ao.misc_lp_ctrl, + MISC_LP_CTRL_RG_ARDMSUS_10, 0x0, + MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL, 0x0, + MISC_LP_CTRL_RG_RIMP_DMSUS_10, 0x0, + MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL, 0x0); + SET32_BITFIELDS(&ch[i_chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPCAL_HW, 0); + } + + impcal_bak = read32(&ch[chn].phy_ao.misc_impcal); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1, MISC_IMP_CTRL1_RG_RIMP_PRE_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_CALI_ENN, 0, + MISC_IMPCAL_IMPCAL_IMPPDP, 1, + MISC_IMPCAL_IMPCAL_IMPPDN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1, + MISC_IMP_CTRL1_RG_IMP_EN, 1, + MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL, 0, + MISC_IMP_CTRL1_RG_RIMP_VREF_EN, 1, + MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL, 1); + udelay(1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPCAL_CALI_EN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVN, 0, + SHU_MISC_IMPCAL1_IMPDRVP, 0); + + for (imp_drv_type drv_type = DRVP; drv_type < IMP_DRV_MAX; drv_type++) { + if (drv_type == ODTP) + continue; + dramc_imp_cal_vref_sel(odt, drv_type); + + switch (drv_type) { + case DRVP: + enp = 0x1; + enn = 0x0; + drvp_result = 0; + break; + case DRVN: + case ODTN: + enp = 0x0; + enn = (drv_type == DRVN) ? 0x0 : 0x1; + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_CALI_ENP, enp); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_CALI_ENN, enn); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVP, drvp_result); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_DRV05, 0); + + cal_res = dramc_sw_imp_cal_result(drv_type); + switch (drv_type) { + case DRVP: + drvp_result = cal_res; + break; + case DRVN: + drvn_result = cal_res; + break; + case ODTN: + odtn_result = cal_res; + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } + } + + imp->result[odt][DRVP] = drvp_result; + imp->result[odt][DRVN] = drvn_result; + imp->result[odt][ODTP] = 0; + imp->result[odt][ODTN] = odtn_result; + + dramc_info("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d\n", + odt, drvp_result, drvn_result, odtn_result); + + write32(&ch[chn].phy_ao.misc_impcal, impcal_bak); + dramc_set_broadcast(bc_bak); +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 184479d..355cc9d 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -73,6 +73,9 @@ emi_mdl_init(cali.emi_config); dramc_set_broadcast(bc_bak);
+ dramc_sw_impedance_cal(ODT_OFF, &cali.impedance); + dramc_sw_impedance_cal(ODT_ON, &cali.impedance); + if (ddr_info->config_dvfs == DRAMC_ENABLE_DVFS) k_shuffle_end = CALI_SEQ_MAX; else
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... PS1, Line 41: u32 change = (drv_type == DRVP) ? 1: 0; spaces required around that ':' (ctx:VxW)
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... PS1, Line 3: string not used ?
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... PS1, Line 6: timer.h> is it used ?
Duan huayang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... PS1, Line 3: string
not used ?
memcpy will call later, so can't remove it. the final file is https://review.coreboot.org/plugins/gitiles/coreboot/+/5c76c7f4ac37023a367f3...
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... PS1, Line 6: timer.h>
is it used ?
wait_us will call later, so can't remove it. the final file is https://review.coreboot.org/plugins/gitiles/coreboot/+/5c76c7f4ac37023a367f3...
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... PS1, Line 3: string
memcpy will call later, so can't remove it. […]
I think we usually want to add header files when adding the code that really uses it. Can you move this to where memcpy will be added?
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... PS1, Line 6: timer.h>
wait_us will call later, so can't remove it. […]
I think we usually want to add header files when adding the code that really uses it. Can you move this to where wait_us will be added?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Julius Werner, Yu-Ping Wu, Duan huayang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44704
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 184 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/2
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
Patch Set 2:
(6 comments)
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... PS2, Line 9: Extra indent
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... PS2, Line 16: u8 vref_tmp = 0; : vref_tmp = imp_vref_sel[odt][drv_type]; Can be combined into one line.
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... PS2, Line 44: switch (drv_type) { This can be simplified by
static const char *const drv_type_str[IMP_DRV_MAX] = { [DRVP] = "DRVP", ... [ODTN] = "ODTN", }; if (drv_type >= IMP_DRV_MAX) die(...); drv_str = drv_type_str[drv_type];
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... PS2, Line 89: dramc_sw_impedance_cal Please add this function to dramc_pi_api.h in this patch.
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... PS2, Line 91: chn Add 'const' for it.
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... PS2, Line 92: cal_res No need to initialize it.
Yidi Lin has uploaded a new patch set (#3) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 177 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/3
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
Patch Set 7:
(5 comments)
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... PS1, Line 3: string
I think we usually want to add header files when adding the code that really uses it. […]
Please remove it.
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... PS1, Line 6: timer.h>
I think we usually want to add header files when adding the code that really uses it. […]
Please remove it.
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... PS2, Line 44: switch (drv_type) {
This can be simplified by […]
Done
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... PS2, Line 91: chn
Add 'const' for it.
Done
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... PS2, Line 92: cal_res
No need to initialize it.
Done
Yidi Lin has uploaded a new patch set (#24) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 177 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/24
Yidi Lin has uploaded a new patch set (#34) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 177 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/34
Yidi Lin has uploaded a new patch set (#36) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 177 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/36
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
Patch Set 36: Code-Review+2
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
Patch Set 40:
(1 comment)
Please address unresolved comments in PS1 and PS2.
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... PS2, Line 89: dramc_sw_impedance_cal
Please add this function to dramc_pi_api.h in this patch.
Ack
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
Patch Set 41:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... PS1, Line 3: string
Please remove it.
Ack
https://review.coreboot.org/c/coreboot/+/44704/1/src/soc/mediatek/mt8192/dra... PS1, Line 6: timer.h>
Please remove it.
Ack
Xi Chen has uploaded a new patch set (#42) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 175 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/42
Xi Chen has uploaded a new patch set (#45) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 175 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/45
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
Patch Set 45:
(6 comments)
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... PS2, Line 9:
Extra indent
Ack
https://review.coreboot.org/c/coreboot/+/44704/2/src/soc/mediatek/mt8192/dra... PS2, Line 16: u8 vref_tmp = 0; : vref_tmp = imp_vref_sel[odt][drv_type];
Can be combined into one line.
Ack
https://review.coreboot.org/c/coreboot/+/44704/45/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44704/45/src/soc/mediatek/mt8192/dr... PS45, Line 7: Extra indent
https://review.coreboot.org/c/coreboot/+/44704/45/src/soc/mediatek/mt8192/dr... PS45, Line 14: u8 vref_tmp = 0; : vref_tmp = imp_vref_sel[odt][drv_type]; Can be combined into one line.
https://review.coreboot.org/c/coreboot/+/44704/45/src/soc/mediatek/mt8192/dr... PS45, Line 66: OK Either "done" or "passed"
https://review.coreboot.org/c/coreboot/+/44704/45/src/soc/mediatek/mt8192/dr... PS45, Line 73: FAIL failed
Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
Patch Set 45:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44704/45/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/44704/45/src/soc/mediatek/mt8192/dr... PS45, Line 7:
Extra indent
Ack
https://review.coreboot.org/c/coreboot/+/44704/45/src/soc/mediatek/mt8192/dr... PS45, Line 14: u8 vref_tmp = 0; : vref_tmp = imp_vref_sel[odt][drv_type];
Can be combined into one line.
Ack
https://review.coreboot.org/c/coreboot/+/44704/45/src/soc/mediatek/mt8192/dr... PS45, Line 66: OK
Either "done" or "passed"
Ack
https://review.coreboot.org/c/coreboot/+/44704/45/src/soc/mediatek/mt8192/dr... PS45, Line 73: FAIL
failed
Ack
Xi Chen has uploaded a new patch set (#46) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 174 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/46
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
Patch Set 46: Code-Review+2
Xi Chen has uploaded a new patch set (#50) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 174 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/50
Xi Chen has uploaded a new patch set (#51) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 174 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/51
Xi Chen has uploaded a new patch set (#52) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 174 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/52
Xi Chen has uploaded a new patch set (#53) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 174 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/53
Xi Chen has uploaded a new patch set (#54) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 174 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44704/54
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44704 )
Change subject: soc/mediatek/mt8192: Do dramc software impedance calibration ......................................................................
soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44704 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c M src/soc/mediatek/mt8192/dramc_pi_main.c 3 files changed, 174 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 1f70e43..a81e532 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -25,7 +25,7 @@
romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c -romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_utility.c +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c new file mode 100644 index 0000000..93988b9 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_pi_calibration_api.c @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> + +static const u8 imp_vref_sel[ODT_MAX][IMP_DRV_MAX] = { + /* DRVP DRVN ODTP ODTN */ + [ODT_OFF] = {0x37, 0x33, 0x00, 0x37}, + [ODT_ON] = {0x3a, 0x33, 0x00, 0x3a}, +}; + +static void dramc_imp_cal_vref_sel(dram_odt_state odt, imp_drv_type drv_type) +{ + u8 vref_tmp = imp_vref_sel[odt][drv_type]; + + switch (drv_type) { + case DRVP: + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP, vref_tmp); + break; + case DRVN: + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN, vref_tmp); + break; + case ODTN: + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN, vref_tmp); + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } +} + +static u32 dramc_sw_imp_cal_result(imp_drv_type drv_type) +{ + u32 drive = 0, cal_res = 0; + u32 change = (drv_type == DRVP) ? 1 : 0; + + static const char *const drv_type_str[IMP_DRV_MAX] = { + [DRVP] = "DRVP", + [DRVN] = "DRVN", + [ODTP] = "ODTP", + [ODTN] = "ODTN", + }; + if (drv_type >= IMP_DRV_MAX) + die("Can't support drv_type %d", drv_type); + + const char *drv_str = drv_type_str[drv_type]; + + for (drive = 0; drive < 32; drive++) { + if (drv_type == DRVP) + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVP, drive); + else if (drv_type == DRVN || drv_type == ODTN) + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVN, drive); + + udelay(1); + cal_res = READ32_BITFIELD(&ch[0].phy_nao.misc_phy_rgs_cmd, + MISC_PHY_RGS_CMD_RGS_RIMPCALOUT); + dramc_dbg("OCD %s=%d ,CALOUT=%d\n", drv_str, drive, cal_res); + + if (cal_res == change) { + dramc_info("%s calibration passed! result=%d\n", drv_str, drive); + break; + } + } + + if (drive == 32) { + drive = 31; + dramc_err("OCD %s calibration failed! %s=%d\n", drv_str, drv_str, drive); + } + + return drive; +} + +void dramc_sw_impedance_cal(dram_odt_state odt, struct dram_impedance *imp) +{ + const u8 chn = 0; + u8 i_chn, enp, enn; + u32 bc_bak, impcal_bak, cal_res; + u32 drvp_result = 0xff, odtn_result = 0xff, drvn_result = 0xff; + + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (i_chn = 0; i_chn < CHANNEL_MAX; i_chn++) { + SET32_BITFIELDS(&ch[i_chn].phy_ao.misc_lp_ctrl, + MISC_LP_CTRL_RG_ARDMSUS_10, 0x0, + MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL, 0x0, + MISC_LP_CTRL_RG_RIMP_DMSUS_10, 0x0, + MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL, 0x0); + SET32_BITFIELDS(&ch[i_chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPCAL_HW, 0); + } + + impcal_bak = read32(&ch[chn].phy_ao.misc_impcal); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1, MISC_IMP_CTRL1_RG_RIMP_PRE_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_CALI_ENN, 0, + MISC_IMPCAL_IMPCAL_IMPPDP, 1, + MISC_IMPCAL_IMPCAL_IMPPDN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1, + MISC_IMP_CTRL1_RG_IMP_EN, 1, + MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL, 0, + MISC_IMP_CTRL1_RG_RIMP_VREF_EN, 1, + MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL, 1); + udelay(1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPCAL_CALI_EN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVN, 0, + SHU_MISC_IMPCAL1_IMPDRVP, 0); + + for (imp_drv_type drv_type = DRVP; drv_type < IMP_DRV_MAX; drv_type++) { + if (drv_type == ODTP) + continue; + dramc_imp_cal_vref_sel(odt, drv_type); + + switch (drv_type) { + case DRVP: + enp = 0x1; + enn = 0x0; + drvp_result = 0; + break; + case DRVN: + case ODTN: + enp = 0x0; + enn = (drv_type == DRVN) ? 0x0 : 0x1; + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } + + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_CALI_ENP, enp); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, + MISC_IMPCAL_IMPCAL_CALI_ENN, enn); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPDRVP, drvp_result); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_DRV05, 0); + + cal_res = dramc_sw_imp_cal_result(drv_type); + switch (drv_type) { + case DRVP: + drvp_result = cal_res; + break; + case DRVN: + drvn_result = cal_res; + break; + case ODTN: + odtn_result = cal_res; + break; + default: + die("Can't support drv_type %d\n", drv_type); + break; + } + } + + imp->result[odt][DRVP] = drvp_result; + imp->result[odt][DRVN] = drvn_result; + imp->result[odt][ODTP] = 0; + imp->result[odt][ODTN] = odtn_result; + + dramc_info("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d\n", + odt, drvp_result, drvn_result, odtn_result); + + write32(&ch[chn].phy_ao.misc_impcal, impcal_bak); + dramc_set_broadcast(bc_bak); +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 48f45d1..fb86305 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -64,6 +64,9 @@ emi_mdl_init(cali.emi_config); dramc_set_broadcast(bc_bak);
+ dramc_sw_impedance_cal(ODT_OFF, &cali.impedance); + dramc_sw_impedance_cal(ODT_ON, &cali.impedance); + if (ddr_info->config_dvfs == DRAMC_ENABLE_DVFS) k_shuffle_end = CALI_SEQ_MAX; else
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build bot (Jenkins) (Code Review) -
CK HU (Code Review)
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Duan huayang (Code Review)
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HAOUAS Elyes (Code Review)
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Hung-Te Lin (Code Review)
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Xi Chen (Code Review)
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Yidi Lin (Code Review)
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Yu-Ping Wu (Code Review)