Change in coreboot[master]: nb/intel/x4x: Add a convenient macro to loop over bytelanes

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22347

Change subject: nb/intel/x4x: Add a convenient macro to loop over bytelanes
......................................................................

nb/intel/x4x: Add a convenient macro to loop over bytelanes

During raminit a lot of procedures need to be done for each bytelane.

Change-Id: Ib9a30ffabaf5c845e962e3e79cf4a20faa1d9857
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/raminit_ddr2.c
M src/northbridge/intel/x4x/rcven.c
M src/northbridge/intel/x4x/x4x.h
3 files changed, 8 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/22347/1

diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index e3d5bb9..9ed4295 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -809,7 +809,7 @@
    int ch, lane, rank;

FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
-		for (lane = 0; lane < 8; lane++) {
+	        FOR_EACH_BYTELANE(lane) {
    		FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank) {
    			switch (s->selected_timings.mem_clk) {
    			case MEM_CLOCK_667MHz:
@@ -871,7 +871,7 @@
    int ch, lane, rank;

FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
-		for (lane = 0; lane < 8; lane++) {
+	        FOR_EACH_BYTELANE(lane) {
    		FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank) {
    			rt_set_dqs(ch, lane, rank,
    				&s->rt_dqs[ch][rank][lane]);
@@ -1148,7 +1148,7 @@
    	reg32 |= s->rcven_t[channel].min_common_coarse << 16;
    	MCHBAR32(0x400 * channel + 0x248) = reg32;

-		for (lane = 0; lane < 8; lane++) {
+	        FOR_EACH_BYTELANE(lane) {
    		medium |= s->rcven_t[channel].medium[lane]
    			<< (lane * 2);
    		coarse_offset |=
diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c
index 1f27208..b1ef034 100644
--- a/src/northbridge/intel/x4x/rcven.c
+++ b/src/northbridge/intel/x4x/rcven.c
@@ -325,7 +325,7 @@
    		addr = test_address(channel, rank);
    		break;
    	}
-		for (lane = 0; lane < 8; lane++) {
+		FOR_EACH_BYTELANE(lane) {
    		printk(BIOS_DEBUG, "Channel %d, Lane %d addr=0x%08x\n",
    			channel, lane, addr);
    		timing[lane].coarse = (s->selected_timings.CAS + 1);
@@ -361,7 +361,7 @@
    	s->rcven_t[channel].min_common_coarse = mincoarse;
    	printk(BIOS_DEBUG, "Receive enable, final timings:\n");
    	/* Normalise coarse */
-		for (lane = 0; lane < 8; lane++) {
+		FOR_EACH_BYTELANE(lane) {
    		if (timing[lane].coarse == 0)
    			reg8 = 0;
    		else
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index 434c5f3..5f2c440 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -161,6 +161,7 @@

#define TOTAL_CHANNELS 2
 #define TOTAL_DIMMS 4
+#define TOTAL_BYTELANES 8
 #define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS)
 #define RAW_CARD_UNPOPULATED 0xff
 #define RAW_CARD_POPULATED 0
@@ -215,6 +216,8 @@
    FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r)
 #define FOR_EACH_POPULATED_RANK(dimms, ch, r) \
    FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r)
+#define FOR_EACH_BYTELANE(l) \
+	for (l = 0; l < TOTAL_BYTELANES; l++)

#define DDR3_MAX_CAS 18