Patch set updated for coreboot: soc/intel/quark: Remove use of EDK-II macros and data types
Lee Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15858
-gerrit
commit 1c1b027a26ff609086712057f8ce608d0aa3dc91 Author: Lee Leahy leroy.p.leahy@intel.com Date: Thu Jul 21 09:17:10 2016 -0700
soc/intel/quark: Remove use of EDK-II macros and data types
Replace the use of ASSERT macro with if/die. Replace the use of UINT32 data type with uint32_t. Replace the use of UINT8 data type with uint8_t.
TEST=Build and run on Galileo Gen2
Change-Id: I0bb7e43ea570f7b20355c5d05675ebf593942e83 Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/soc/intel/quark/chip.c | 15 +++++++----- src/soc/intel/quark/chip.h | 52 ++++++++++++++++++++-------------------- src/soc/intel/quark/i2c.c | 20 ++++++++++------ src/soc/intel/quark/memmap.c | 2 +- src/soc/intel/quark/reg_access.c | 12 ++++++---- 5 files changed, 57 insertions(+), 44 deletions(-)
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 30ab48a..07eca13 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -101,19 +101,22 @@ static const struct reg_script thermal_init_script[] = { static void chip_init(void *chip_info) { /* Validate the temperature settings */ - ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255); - ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS - > PLATFORM_CATASTROPHIC_CLEAR_CELSIUS); + if(PLATFORM_CATASTROPHIC_TRIP_CELSIUS > 255) + die("PLATFORM_CATASTROPHIC_TRIP_CELSIUS > 255\n"); + if(PLATFORM_CATASTROPHIC_TRIP_CELSIUS + <= PLATFORM_CATASTROPHIC_CLEAR_CELSIUS) + die("PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= PLATFORM_CATASTROPHIC_CLEAR_CELSIUS\n");
/* Set the temperature settings */ reg_script_run(thermal_init_script);
/* Verify that the thermal configuration is locked */ - ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) + if((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) & (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) - == (TS_LOCK_THRM_CTRL_REGS_ENABLE - | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); + != (TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) + die("(reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) & (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) != (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)\n");
/* Perform silicon specific init. */ if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h index 66105ea..b239631 100644 --- a/src/soc/intel/quark/chip.h +++ b/src/soc/intel/quark/chip.h @@ -47,70 +47,70 @@ struct soc_intel_quark_config { * the FSP PCD field name. */
- UINT32 FspReservedMemoryLength; /* FSP reserved memory in bytes */ + uint32_t FspReservedMemoryLength; /* FSP reserved memory in bytes */
- UINT32 Flags; /* Bitmap of MRC_FLAG_XXX defs above */ - UINT32 tRAS; /* ACT to PRE command period in picoseconds */ + uint32_t Flags; /* Bitmap of MRC_FLAG_XXX defs above */ + uint32_t tRAS; /* ACT to PRE command period in picoseconds */
/* Delay from start of internal write transaction to internal read * command in picoseconds */ - UINT32 tWTR; + uint32_t tWTR;
/* ACT to ACT command period (JESD79 specific to page size 1K/2K) in * picoseconds */ - UINT32 tRRD; + uint32_t tRRD;
/* Four activate window (JESD79 specific to page size 1K/2K) in * picoseconds */ - UINT32 tFAW; - UINT8 DramWidth; /* 0=x8, 1=x16, others=RESERVED */ + uint32_t tFAW; + uint8_t DramWidth; /* 0=x8, 1=x16, others=RESERVED */
/* 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU * support 1066 memory */ - UINT8 DramSpeed; - UINT8 DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */ + uint8_t DramSpeed; + uint8_t DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */
/* bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED */ - UINT8 RankMask; - UINT8 ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */ - UINT8 ChanWidth; /* 1=x16, others=RESERVED */ + uint8_t RankMask; + uint8_t ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */ + uint8_t ChanWidth; /* 1=x16, others=RESERVED */
/* 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED */ - UINT8 AddrMode; + uint8_t AddrMode;
/* 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE */ - UINT8 SrInt; - UINT8 SrTemp; /* 0=normal, 1=extended, others=RESERVED */ + uint8_t SrInt; + uint8_t SrTemp; /* 0=normal, 1=extended, others=RESERVED */
/* 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver * impedance control. */ - UINT8 DramRonVal; - UINT8 DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */ - UINT8 DramRttWrVal; /* 0=off others=RESERVED */ + uint8_t DramRonVal; + uint8_t DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */ + uint8_t DramRttWrVal; /* 0=off others=RESERVED */
/* 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */ - UINT8 SocRdOdtVal; - UINT8 SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */ - UINT8 SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */ + uint8_t SocRdOdtVal; + uint8_t SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */ + uint8_t SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */
/* 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED */ - UINT8 DramDensity; - UINT8 tCL; /* DRAM CAS Latency in clocks */ + uint8_t DramDensity; + uint8_t tCL; /* DRAM CAS Latency in clocks */
/* ECC scrub interval in miliseconds 1..255 (0 works as feature * disable) */ - UINT8 EccScrubInterval; + uint8_t EccScrubInterval;
/* Number of 32B blocks read for ECC scrub 2..16 */ - UINT8 EccScrubBlkSize; + uint8_t EccScrubBlkSize;
- UINT8 SmmTsegSize; /* SMM size in MiB */ + uint8_t SmmTsegSize; /* SMM size in MiB */ };
extern struct chip_operations soc_ops; diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 118cbea..9e02915 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -63,9 +63,12 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) i2c_disable(regs);
/* Set the slave address */ - ASSERT (count > 0); - ASSERT (segments != NULL); - ASSERT (segments->read == 0); + if (count == 0) + die("ERROR - count == 0\n"); + if (segments == NULL) + die("ERROR - segments == NULL\n"); + if (segments->read != 0) + die("ERROR - segments->read != \n");
/* Clear the start and stop detection */ status = regs->ic_clr_start_det; @@ -98,9 +101,12 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) while (count-- > 0) { buffer = segments->buf; length = segments->len; - ASSERT (buffer != NULL); - ASSERT (length >= 1); - ASSERT (segments->chip = chip); + if (buffer == NULL) + die("ERROR - buffer == NULL\n"); + if (length < 1) + die("ERROR - length < 1\n"); + if (segments->chip != chip) + die("ERROR - segments->chip != chip\n");
if (segments->read) { /* Place read commands into the FIFO */ @@ -166,7 +172,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) /* Finish reading the data bytes */ while (read_length > 0) { status = regs->ic_status; - *buffer++ = (UINT8)regs->ic_data_cmd; + *buffer++ = (uint8_t)regs->ic_data_cmd; read_length--; bytes_transferred++; status = regs->ic_status; diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index 351fab7..f880443 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -26,7 +26,7 @@ size_t mmap_region_granularity(void)
void *cbmem_top(void) { - UINT32 top_of_memory; + uint32_t top_of_memory;
/* Determine the TSEG base */ top_of_memory = reg_host_bridge_unit_read(QNC_MSG_FSBIC_REG_HSMMC); diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 4f14173..7383ddd 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -26,7 +26,8 @@ static uint16_t get_gpe0_address(uint32_t reg_address)
/* Get the GPE0 base address */ gpe0_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GPE0BLK); - ASSERT (gpe0_base_address >= 0x80000000); + if (gpe0_base_address < 0x80000000) + die("ERROR - gpe0_base_address < 0x80000000\n"); gpe0_base_address &= B_QNC_LPC_GPE0BLK_MASK;
/* Return the GPE0 register address */ @@ -40,7 +41,8 @@ static uint32_t *get_gpio_address(uint32_t reg_address) /* Get the GPIO base address */ gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_1); gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - ASSERT (gpio_base_address != 0x00000000); + if (gpio_base_address == 0) + die("ERROR - gpio_base_address == 0\n");
/* Return the GPIO register address */ return (uint32_t *)(gpio_base_address + reg_address); @@ -53,7 +55,8 @@ void *get_i2c_address(void) /* Get the GPIO base address */ gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_0); gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - ASSERT (gpio_base_address != 0x00000000); + if (gpio_base_address == 0) + die("ERROR - gpio_base_address == 0\n");
/* Return the GPIO register address */ return (void *)gpio_base_address; @@ -65,7 +68,8 @@ static uint16_t get_legacy_gpio_address(uint32_t reg_address)
/* Get the GPIO base address */ gpio_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GBA_BASE); - ASSERT (gpio_base_address >= 0x80000000); + if (gpio_base_address < 0x80000000) + die("ERROR - gpio_base_address < 0x80000000\n"); gpio_base_address &= B_QNC_LPC_GPA_BASE_MASK;
/* Return the GPIO register address */
-
Lee Leahy