York Yang (york.yang@intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12095
-gerrit
commit 7eebcbed9039704d3774ab3c719286deca0cdae8 Author: York Yang york.yang@intel.com Date: Mon Oct 19 13:35:21 2015 -0700
intel/fsp_baytrail: Load APs microcode in baytrail_init_cpus
Load microcode to APs when performing baytrail_init_cpus. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load.
Change-Id: I7b7c0f43da0d149048ae5a8fd547828f42de04fd Signed-off-by: York Yang york.yang@intel.com --- src/soc/intel/fsp_baytrail/Makefile.inc | 1 + src/soc/intel/fsp_baytrail/cpu.c | 4 ++-- src/soc/intel/fsp_baytrail/ramstage.c | 1 + 3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 7370830..65ff323 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -26,6 +26,7 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache +subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../lib/fsp subdirs-y += fsp diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 8fe1df3..c4416b9 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -80,11 +80,11 @@ void baytrail_init_cpus(device_t dev) setup_lapic();
mp_params.num_cpus = pattrs->num_cpus, - mp_params.parallel_microcode_load = 0, + mp_params.parallel_microcode_load = 1, mp_params.adjust_apic_id = adjust_apic_id; mp_params.flight_plan = &mp_steps[0]; mp_params.num_records = ARRAY_SIZE(mp_steps); - mp_params.microcode_pointer = 0; + mp_params.microcode_pointer = pattrs->microcode_patch;
if (mp_init(cpu_bus, &mp_params)) { printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 429039e..075af05 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -93,6 +93,7 @@ static void fill_in_pattrs(void) attrs->stepping += STEP_A0; }
+ attrs->microcode_patch = intel_microcode_find(); attrs->address_bits = cpuid_eax(0x80000008) & 0xff; detect_num_cpus(attrs);