[M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure LP5 memory parts

[Subrata Banik (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Harsha B R, Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar, Usha P.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69741 )

Change subject: mb/intel/mtlrvp: Add romstage and configure LP5 memory parts
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Patch Set 10:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/69741/comment/39d17f31_dea003f0 
PS10, Line 13: FW_NAME=mtlrvp_p emerge-rex coreboot chromeos-bootimage
Note: building the MTLRVP can't be a test statement, the purpose of the test is to ensure the code that you have added is actually meant to fix something or enable some feature. Adding a test statement like this would mean nothing IMO.