PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37265 )
Change subject: soc/intel/cannonlake: Fix compilation ......................................................................
soc/intel/cannonlake: Fix compilation
change MicrocodeRegionLength to MicrocodeRegionSize as per coffeelake FsptUpd.h.
TEST= Build and boot test on coffeelake RVP.
Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a Signed-off-by: Praveen Hodagatta Pranesh praveenx.hodagatta.pranesh@intel.com --- M src/soc/intel/cannonlake/bootblock/bootblock.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37265/1
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 9f85397..6a6dd8b 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -39,10 +39,10 @@ * All SoC since Gen-4 has above mechanism in place to load microcode * even before hitting CPU reset vector. Hence skipping FSP-T loading * microcode after CPU reset by passing '0' value to - * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionSize. */ .MicrocodeRegionBase = 0, - .MicrocodeRegionLength = 0, + .MicrocodeRegionSize = 0, .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37265 )
Change subject: soc/intel/cannonlake: Fix compilation ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37265/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37265/1//COMMIT_MSG@12 PS1, Line 12: Build Please be a bit more specific using FSP-T is not default.
Hello Patrick Rudolph, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37265
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Fix compilation ......................................................................
soc/intel/cannonlake: Fix compilation
change MicrocodeRegionLength to MicrocodeRegionSize as per coffeelake FsptUpd.h.
TEST= Build with FSP_CAR selected and boot test on coffeelake RVP.
Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a Signed-off-by: Praveen Hodagatta Pranesh praveenx.hodagatta.pranesh@intel.com --- M src/soc/intel/cannonlake/bootblock/bootblock.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37265/2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37265 )
Change subject: soc/intel/cannonlake: Fix compilation ......................................................................
Patch Set 2: Code-Review+2
PraveenX Hodagatta Pranesh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37265 )
Change subject: soc/intel/cannonlake: Fix compilation ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37265/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37265/1//COMMIT_MSG@12 PS1, Line 12: Build
Please be a bit more specific using FSP-T is not default.
Done
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37265 )
Change subject: soc/intel/cannonlake: Fix compilation ......................................................................
Patch Set 2: Code-Review+1
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37265 )
Change subject: soc/intel/cannonlake: Fix compilation ......................................................................
Patch Set 2:
(2 comments)
Please add a separate CL that has jenkins buildtest CONFIG_FSP_CAR. Do this by adding a config to configs/.
https://review.coreboot.org/c/coreboot/+/37265/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37265/2//COMMIT_MSG@9 PS2, Line 9: change Capital letter.
https://review.coreboot.org/c/coreboot/+/37265/2//COMMIT_MSG@12 PS2, Line 12: FSP_CAR CONFIG_FSP_CAR. Add this to the CL title.
Hello Patrick Rudolph, Subrata Banik, Lean Sheng Tan, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37265
to look at the new patch set (#3).
Change subject: soc/intel/cannonlake: Fix compilation ......................................................................
soc/intel/cannonlake: Fix compilation
Change MicrocodeRegionLength to MicrocodeRegionSize as per coffeelake FsptUpd.h.
TEST= Build with USE_CANNONLAKE_FSP_CAR selected and boot test on coffeelake RVP.
Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a Signed-off-by: Praveen Hodagatta Pranesh praveenx.hodagatta.pranesh@intel.com --- M src/soc/intel/cannonlake/bootblock/bootblock.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37265/3
Hello Patrick Rudolph, Subrata Banik, Lean Sheng Tan, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37265
to look at the new patch set (#4).
Change subject: soc/intel/cannonlake: Fix compilation ......................................................................
soc/intel/cannonlake: Fix compilation
Change MicrocodeRegionLength to MicrocodeRegionSize as per coffeelake FsptUpd.h.
TEST= Build with CONFIG_USE_CANNONLAKE_FSP_CAR selected and boot test on coffeelake RVP.
Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a Signed-off-by: Praveen Hodagatta Pranesh praveenx.hodagatta.pranesh@intel.com --- M src/soc/intel/cannonlake/bootblock/bootblock.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37265/4
PraveenX Hodagatta Pranesh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37265 )
Change subject: soc/intel/cannonlake: Fix compilation ......................................................................
Patch Set 4:
Patch Set 2:
(2 comments)
Please add a separate CL that has jenkins buildtest CONFIG_FSP_CAR. Do this by adding a config to configs/.
some thing like this https://review.coreboot.org/c/coreboot/+/37275 ?. please correct me if i did wrong way, Thanks
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37265 )
Change subject: soc/intel/cannonlake: Fix compilation ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37265 )
Change subject: soc/intel/cannonlake: Fix compilation ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37265/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37265/2//COMMIT_MSG@9 PS2, Line 9: change
Capital letter.
Done
https://review.coreboot.org/c/coreboot/+/37265/2//COMMIT_MSG@12 PS2, Line 12: FSP_CAR
CONFIG_FSP_CAR. Add this to the CL title.
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37265 )
Change subject: soc/intel/cannonlake: Fix compilation ......................................................................
soc/intel/cannonlake: Fix compilation
Change MicrocodeRegionLength to MicrocodeRegionSize as per coffeelake FsptUpd.h.
TEST= Build with CONFIG_USE_CANNONLAKE_FSP_CAR selected and boot test on coffeelake RVP.
Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a Signed-off-by: Praveen Hodagatta Pranesh praveenx.hodagatta.pranesh@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37265 Reviewed-by: Subrata Banik subrata.banik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/cannonlake/bootblock/bootblock.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 9f85397..6a6dd8b 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -39,10 +39,10 @@ * All SoC since Gen-4 has above mechanism in place to load microcode * even before hitting CPU reset vector. Hence skipping FSP-T loading * microcode after CPU reset by passing '0' value to - * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionSize. */ .MicrocodeRegionBase = 0, - .MicrocodeRegionLength = 0, + .MicrocodeRegionSize = 0, .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,
-
Arthur Heymans (Code Review) -
Lean Sheng Tan (Code Review)
-
Patrick Georgi (Code Review)
-
PraveenX Hodagatta Pranesh (Code Review)
-
Subrata Banik (Code Review)