Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30774
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
mb/google/hatch: Configure miscellaneous features
set SaGv = 3 , To set System Agent dynamic frequency support as FixedHigh set HeciEnabled = 1, To Enable heci communication set VmxEnable = 1, To Enable Virtual-Machine Extension support set speed_shift_enable = 1 To Enable Speed Shift Technology support set s0ix_enable = 0, To Disable active idle state support. Will make it Enable when platform will be in stable stage set dptf_enable = 0, To Disable Dynamic Platform Thermal Framework support. Will make it Enable when platform will be in stable stage set dmipwroptimize = 1 , To Enable DMI Power Optimizer on PCH side
Change-Id: Iea90a65a77ef5e45a802cfe6fd31e1921163b02b Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30774/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 45e8421..7104fd4 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -49,6 +49,13 @@ register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" register "satapwroptimize" = "1" + register "SaGv" = "3" + register "HeciEnabled" = "1" + register "VmxEnable" = "1" + register "speed_shift_enable" = "1" + register "s0ix_enable" = "0" + register "dptf_enable" = "0" + register "dmipwroptimize" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1
Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 4:
(7 comments)
https://review.coreboot.org/#/c/30774/1/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/1/src/mainboard/google/hatch/variants/... PS1, Line 52: 3
check for a macro in chip. […]
That SaGV enum was not applicable here because it has 5 values as below 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled for CML we don't use FixedMid so in CML FSP we have below options 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled
I pushed following patch to correct SaGv options for all Soc once that change is merged we can use SaGv_Enable in place of 3
https://review.coreboot.org/c/coreboot/+/30917/
https://review.coreboot.org/#/c/30774/1/src/mainboard/google/hatch/variants/... PS1, Line 53: HeciEnabled
This option gives a choice for enabling/disabling Heci function to the mainboard folks. […]
Done
https://review.coreboot.org/#/c/30774/1/src/mainboard/google/hatch/variants/... PS1, Line 54: VmxEnable
+1. […]
Done
https://review.coreboot.org/#/c/30774/1/src/mainboard/google/hatch/variants/... PS1, Line 55: register "speed_shift_enable" = "1"
add a description as below […]
I will add comment
https://review.coreboot.org/#/c/30774/1/src/mainboard/google/hatch/variants/... PS1, Line 56: s0ix_enable
# Enable S0ix
I will add comment
https://review.coreboot.org/#/c/30774/1/src/mainboard/google/hatch/variants/... PS1, Line 57: dptf_enable
don't enable it now without adding proper ASL entries. […]
This is place holder option whenever we will add ASL we will enable this bit
https://review.coreboot.org/#/c/30774/1/src/mainboard/google/hatch/variants/... PS1, Line 58: dmipwroptimize
Looks like this option doesn't have any effect, must be removed.
Done
Hello Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30774
to look at the new patch set (#5).
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
mb/google/hatch: Configure miscellaneous features
set SaGv = SaGv_Enabled , To Enable System Agent dynamic frequency support set HeciEnabled = 1, To Enable heci communication set VmxEnable = 1, To Enable Virtual-Machine Extension support set speed_shift_enable = 1 To Enable Speed Shift Technology support set s0ix_enable = 0, To Disable active idle state support. Will make it Enable when platform will be in stable stage set dptf_enable = 0, To Disable Dynamic Platform Thermal Framework support. Will make it Enable when platform will be in stable stage
Change-Id: Iea90a65a77ef5e45a802cfe6fd31e1921163b02b Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30774/5
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/30774/5/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/5/src/mainboard/google/hatch/variants/... PS5, Line 59: # Enable S0ix : register "s0ix_enable" = "0" : # Enable Dynamic Platform Thermal Framework support : register "dptf_enable" = "0" anything is 0, u don't need to set. its default set to 0
Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/30774/5/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/5/src/mainboard/google/hatch/variants/... PS5, Line 59: # Enable S0ix : register "s0ix_enable" = "0" : # Enable Dynamic Platform Thermal Framework support : register "dptf_enable" = "0"
anything is 0, u don't need to set. […]
This is place holder option whenever we will add ASL we will enable dptf_enable and when platform get stable we will enable s0ix_enable.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/30774/5/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/5/src/mainboard/google/hatch/variants/... PS5, Line 59: # Enable S0ix : register "s0ix_enable" = "0" : # Enable Dynamic Platform Thermal Framework support : register "dptf_enable" = "0"
This is place holder option whenever we will add ASL we will enable dptf_enable and when platform ge […]
doesn't make sense to create some placeholder like this. delete it.
enable it as and when it required.
Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/30774/5/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/5/src/mainboard/google/hatch/variants/... PS5, Line 59: # Enable S0ix : register "s0ix_enable" = "0" : # Enable Dynamic Platform Thermal Framework support : register "dptf_enable" = "0"
doesn't make sense to create some placeholder like this. delete it. […]
okay I will remove it
Hello Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30774
to look at the new patch set (#6).
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
mb/google/hatch: Configure miscellaneous features
set SaGv = SaGv_Enabled , To Enable System Agent dynamic frequency support set HeciEnabled = 1, To Enable heci communication set VmxEnable = 1, To Enable Virtual-Machine Extension support set speed_shift_enable = 1 To Enable Speed Shift Technology support
Change-Id: Iea90a65a77ef5e45a802cfe6fd31e1921163b02b Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30774/6
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/30774/6/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/6/src/mainboard/google/hatch/variants/... PS6, Line 56: VmxEnable can u check if this value is taking any real effect ?
Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/30774/6/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/6/src/mainboard/google/hatch/variants/... PS6, Line 56: VmxEnable
can u check if this value is taking any real effect ?
I will get back to you with more information.
Hello Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30774
to look at the new patch set (#7).
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
mb/google/hatch: Configure miscellaneous features
set SaGv = SaGv_Enabled , To Enable System Agent dynamic frequency support set HeciEnabled = 1, To Enable heci communication set speed_shift_enable = 1 To Enable Speed Shift Technology support
Change-Id: Iea90a65a77ef5e45a802cfe6fd31e1921163b02b Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30774/7
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 7: Code-Review+2
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/30774/6/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/6/src/mainboard/google/hatch/variants/... PS6, Line 56: VmxEnable
I will get back to you with more information.
I think this was clarified earlier, if FSP skips the MP init (which is the case for Hatch) this setting has no effect. we should be removing this and using the VMX configuration being done in coreboot MP init. i.e., select SOC_INTEL_COMMON_BLOCK_VMX and call vmx_configure() on all cpus.
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 7: Code-Review+2
Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/30774/6/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/6/src/mainboard/google/hatch/variants/... PS6, Line 56: VmxEnable
I think this was clarified earlier, if FSP skips the MP init (which is the case for Hatch) this sett […]
done
Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/30774/6/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/6/src/mainboard/google/hatch/variants/... PS6, Line 56: VmxEnable
done
which means, You have to push a separate patch for enabling VMX.
Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/30774/6/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/6/src/mainboard/google/hatch/variants/... PS6, Line 56: VmxEnable
which means, You have to push a separate patch for enabling VMX.
OK I will push separate patch for VMX enabling.
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
mb/google/hatch: Configure miscellaneous features
set SaGv = SaGv_Enabled , To Enable System Agent dynamic frequency support set HeciEnabled = 1, To Enable heci communication set speed_shift_enable = 1 To Enable Speed Shift Technology support
Change-Id: Iea90a65a77ef5e45a802cfe6fd31e1921163b02b Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com Reviewed-on: https://review.coreboot.org/c/30774 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 8dd2d84..5b777f8 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -48,6 +48,12 @@ register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" register "satapwroptimize" = "1" + # Enable System Agent dynamic frequency + register "SaGv" = "SaGv_Enabled" + # Enable heci communication + register "HeciEnabled" = "1" + # Enable Speed Shift Technology support + register "speed_shift_enable" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... PS8, Line 53: # Enable heci communication : register "HeciEnabled" = "1" This is not correct.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... PS8, Line 53: # Enable heci communication : register "HeciEnabled" = "1"
This is not correct.
Ack, refer to CB:31097
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... PS8, Line 53: # Enable heci communication : register "HeciEnabled" = "1"
This is not correct.
i didn't get what is not correct here ?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... PS8, Line 53: # Enable heci communication : register "HeciEnabled" = "1"
i didn't get what is not correct here ?
We do not want to keep the HECI interface up when jumping to OS. That is what is done on all older platforms.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... PS8, Line 53: # Enable heci communication : register "HeciEnabled" = "1"
We do not want to keep the HECI interface up when jumping to OS. […]
this is just to ensure that FSP don't disable CSME interface before sending EOP which is not recommended.
Please check lspci on your any WHL based device, i hope you will see CSME bus 0, device 0x16, function 0 is default enable with and without this changes. There is some open which we need to address in order to function disable CSME before booting to OS after sending EOP.
Kindly look at CNL implementation of function disabling of CSME. If you have CNL device, you won't see CSME in lspci even this UPD is enable. The concern is that same implementation as CNL won't be applied here for CFL and WHL platform.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... PS8, Line 53: # Enable heci communication : register "HeciEnabled" = "1"
this is just to ensure that FSP don't disable CSME interface before sending EOP which is not recommended.
On CNL/CFL/WHL, this is not used to set any UPD for FSP. It is used to call pch_disable_heci: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/cannonlake/...
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... PS8, Line 53: # Enable heci communication : register "HeciEnabled" = "1"
this is just to ensure that FSP don't disable CSME interface before sending EOP which is not recom […]
oh yes, i just realized that Intel don't claim to disable CSME in boot flow hence there shouldn't be any UPD to disable CSME in boot flow.
but my concern is that hecienabled = 0 might not help here as well. can you please check ?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... PS8, Line 53: # Enable heci communication : register "HeciEnabled" = "1"
oh yes, i just realized that Intel don't claim to disable CSME in boot flow hence there shouldn't be […]
Currently, hecienabled=1 causes a boot hang. Shelley is looking into it.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 8:
(1 comment)
@Aamir/Rizwan: any comment on this observation where hecienable=1 causing hang?
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... PS8, Line 53: # Enable heci communication : register "HeciEnabled" = "1"
Currently, hecienabled=1 causes a boot hang. Shelley is looking into it.
I thought Aamir has verified this changes during PO.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... PS8, Line 53: # Enable heci communication : register "HeciEnabled" = "1"
I thought Aamir has verified this changes during PO.
Sorry, I meant hecienabled=0 is causing a hang.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... PS8, Line 53: # Enable heci communication : register "HeciEnabled" = "1"
Sorry, I meant hecienabled=0 is causing a hang.
that is expected as i told in previous comment, same CNL logic to function disable CSME don't be applicable for WHL platform as i understood.
this should be a RCR or feature request to work on.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... PS8, Line 53: # Enable heci communication : register "HeciEnabled" = "1"
that is expected as i told in previous comment, same CNL logic to function disable CSME don't be app […]
Internal bug here: b/123413775. Can you please add appropriate folks to drive this forward?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... PS8, Line 53: # Enable heci communication : register "HeciEnabled" = "1"
Internal bug here: b/123413775. […]
can you please add me there
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30774 )
Change subject: mb/google/hatch: Configure miscellaneous features ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/30774/8/src/mainboard/google/hatch/variants/... PS8, Line 53: # Enable heci communication : register "HeciEnabled" = "1"
can you please add me there
done.
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Angel Pons (Code Review) -
Furquan Shaikh (Code Review)
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Patrick Georgi (Code Review)
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Rizwan Qureshi (Code Review)
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Ronak Kanabar (Code Review)
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Subrata Banik (Code Review)