Change in coreboot[master]: soc/intel/tigerlake: Simplify FSP chipset lockdown configuration - coreboot-gerrit

3 May 2021


      Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.
 Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52844 )
Change subject: soc/intel/tigerlake: Simplify FSP chipset lockdown configuration
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/52844/comment/fe131bf5_f60355cc 
PS5, Line 205: uint8_t
...
nit: const
Done
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/52844
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0580fb3ec9daafac273dcb091f48ce403c22e8f8
Gerrit-Change-Number: 52844
Gerrit-PatchSet: 6
Gerrit-Owner:  Felix Singer felixsinger@posteo.net
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Attention: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-Attention: Patrick Rudolph siro@das-labor.org
Gerrit-Comment-Date: Mon, 03 May 2021 21:04:30 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-MessageType: comment