Change in coreboot[master]: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting
Duan huayang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
soc/mediatek/mt8183: Fix some programming errors of DRAMC setting
Fix some programming errors.
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui
Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 3 files changed, 56 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42193/1
diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index cb64e50..082f6bb 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -57,9 +57,9 @@ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { setbits32(&ch[chn].ao.dvfsdll, 0x1 << 5); setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 29); - clrsetbits32(&ch[0].ao.shuctrl2, 0x7f, dll_idle); + clrsetbits32(&ch[chn].ao.shuctrl2, 0x7f, dll_idle);
- setbits32(&ch[0].phy.misc_ctrl0, 0x3 << 19); + setbits32(&ch[chn].phy.misc_ctrl0, 0x3 << 19); setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24); setbits32(&ch[chn].ao.dvfsdll, 0x1 << 7); } @@ -890,12 +890,11 @@
clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x0 << 2) | (0x3 << 8)); - clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x4 << 20); - - clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x4 << 20); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x2 << 4) | (0x0 << 7) | (0x0 << 13)); - clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20); - clrbits32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13)); + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x4 << 20); + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 7) | (0x1 << 13));
for (size_t r = 0; r < 2; r++) { int value = ((r == 0) ? 0x1a : 0x26); @@ -949,11 +948,11 @@
clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x1 << 2) | (0x4 << 8)); - clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x1 << 4) | (0x1 << 7) | (0x1 << 13)); - clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&ch[0].phy.b[1].dq[7], + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 7) | (0x1 << 13), (0x1 << 7) | (0x1 << 13));
for (size_t r = 0; r < 2; r++) { @@ -1057,7 +1056,7 @@ clrsetbits32(&ch[0].phy.ca_cmd[6], (0x1 << 6) | (0x3 << 14) | (0x1 << 16), (0x0 << 6) | (0x0 << 14) | (0x0 << 16));
- clrbits32(&ch[0].phy.pll3, 0x1 < 0); + clrbits32(&ch[0].phy.pll3, 0x1 << 0); setbits32(&ch[0].phy.b[0].dq[3], 0x1 << 3); setbits32(&ch[0].phy.b[1].dq[3], 0x1 << 3);
@@ -1088,7 +1087,11 @@
for (size_t b = 0; b < 2; b++) setbits32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10)); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); setbits32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0); + setbits32(&ch[1].phy.shu[0].ca_dll[0], 0x1 << 0); + dramc_set_broadcast(DRAMC_BROADCAST_ON);
for (size_t b = 0; b < 2; b++) clrsetbits32(&ch[0].phy.shu[0].b[b].dll[0], diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 5bffc42..580d435 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -48,10 +48,12 @@ broadcast_bak = dramc_get_broadcast(); dramc_set_broadcast(DRAMC_BROADCAST_OFF);
- clrbits32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); - write32(&ch[0].phy.misc_spm_ctrl2, 0x0); - write32(&ch[0].phy.misc_spm_ctrl0, 0x0); - clrbits32(&ch[0].ao.impcal, 0x1 << 31); + for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { + clrbits32(&ch[chn].phy.misc_spm_ctrl1, 0xf << 0); + write32(&ch[chn].phy.misc_spm_ctrl2, 0x0); + write32(&ch[chn].phy.misc_spm_ctrl0, 0x0); + clrbits32(&ch[chn].ao.impcal, 0x1 << 31); + }
impcal_bak = read32(&ch[0].ao.impcal); dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVP); @@ -92,7 +94,7 @@ if (term == ODT_ON) setbits32(&ch[0].ao.impcal, 0x1 << 21); clrsetbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11, - DRVP_result << 4 | 0x1f << 11); + DRVP_result << 4 ); clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3);
for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) { @@ -151,9 +153,6 @@ sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2]; sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3];
- clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3); - dramc_sw_imp_cal_vref_sel(dq_term, IMPCAL_STAGE_DRVP); - /* DQ */ clrsetbits32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0), (sw_impedance[dq_term][0] << 5) | @@ -203,7 +202,10 @@ SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[0], SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 0);
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF); clrsetbits32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); + clrsetbits32(&ch[1].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); + dramc_set_broadcast(DRAMC_BROADCAST_ON); }
static void transfer_pll_to_spm_control(void) diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index b557550..0f91d18 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -366,12 +366,30 @@ clrsetbits32(&ch[chn].ao.stbcal, 0x1 << 22, (on ? 0x1 : 0) << 22); }
-static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn) +static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn, u8 freq_group) { + u8 dvs_delay; + struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[0];
- clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, 0x3 << 20); + switch (freq_group) { + case LP4X_DDR1600: + dvs_delay = 5; + break; + case LP4X_DDR2400: + dvs_delay = 4; + break; + case LP4X_DDR3200: + case LP4X_DDR3600: + dvs_delay = 3; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, dvs_delay << 20); + clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, dvs_delay << 20); clrbits32(&shu->b[0].dq[7], (0x1 << 12) | (0x1 << 13)); clrbits32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13)); } @@ -409,7 +427,13 @@ dramc_hw_gating_onoff(chn, false); clrbits32(&ch[chn].ao.stbcal2, 0x1 << 28);
- setbits32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11)); + for (size_t r = 0; r < 2; r++) { + for (size_t b = 0; b < 2; b++) + clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2], + (0x1 << 28) | (0x1 << 23) | (0x3 << 30)); + clrbits32(&ch[chn].phy.r0_ca_rxdvs[2], 0x3 << 30); + } + setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 7); clrbits32(&ch[chn].ao.refctrl0, 0x1 << 18); clrbits32(&ch[chn].ao.mrs, 0x3 << 24); setbits32(&ch[chn].ao.mpc_option, 0x1 << 17); @@ -417,21 +441,14 @@ clrsetbits32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0); clrsetbits32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0);
- dramc_rx_input_delay_tracking_init_by_freq(chn); + dramc_rx_input_delay_tracking_init_by_freq(chn, freq_group);
setbits32(&ch[chn].ao.dummy_rd, 0x1 << 25); setbits32(&ch[chn].ao.drsctrl, 0x1 << 0); if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) - clrbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); + clrbits32(&ch[chn].ao.shu[0].drving[0], 0x1 << 31); else - setbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); - } - - for (size_t r = 0; r < 2; r++) { - for (size_t b = 0; b < 2; b++) - clrbits32(&ch[0].phy.r[r].b[b].rxdvs[2], - (0x1 << 28) | (0x1 << 23) | (0x3 << 30)); - clrbits32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30); + setbits32(&ch[chn].ao.shu[0].drving[0], 0x1 << 31); } }
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42193/1/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/42193/1/src/soc/mediatek/mt8183/dra... PS1, Line 97: DRVP_result << 4 ); space prohibited before that close parenthesis ')'
Hello Julius Werner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42193
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
soc/mediatek/mt8183: Fix some programming errors of DRAMC setting
Fix some programming errors.
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui
Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 3 files changed, 56 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42193/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG@7 PS2, Line 7: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting I’d prefer a more specific commit message summary. Maybe split the commit up.
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG@9 PS2, Line 9: Fix some programming errors. Please elaborate.
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG@13 PS2, Line 13: TEST=Boots correctly on Kukui … as before, right?
Or did you see errors before?
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42193/2/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/42193/2/src/soc/mediatek/mt8183/dra... PS2, Line 894: (0x3 << 4) | (0x1 << 7) | (0x1 << 13), Move to next line.
https://review.coreboot.org/c/coreboot/+/42193/2/src/soc/mediatek/mt8183/dra... PS2, Line 952: (0x3 << 4) | (0x1 << 7) | (0x1 << 13), Move to next line.
https://review.coreboot.org/c/coreboot/+/42193/2/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/42193/2/src/soc/mediatek/mt8183/dra... PS2, Line 51: size_t u8
Hello build bot (Jenkins), Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42193
to look at the new patch set (#3).
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
soc/mediatek/mt8183: Fix some programming errors of DRAMC setting
Fix some programming errors.
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui
Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 3 files changed, 58 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42193/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
Patch Set 3:
(6 comments)
https://review.coreboot.org/c/coreboot/+/42193/3/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/42193/3/src/soc/mediatek/mt8183/dra... PS3, Line 893: clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], trailing whitespace
https://review.coreboot.org/c/coreboot/+/42193/3/src/soc/mediatek/mt8183/dra... PS3, Line 894: (0x3 << 4) | (0x1 << 7) | (0x1 << 13), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/42193/3/src/soc/mediatek/mt8183/dra... PS3, Line 894: (0x3 << 4) | (0x1 << 7) | (0x1 << 13), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/42193/3/src/soc/mediatek/mt8183/dra... PS3, Line 952: clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], trailing whitespace
https://review.coreboot.org/c/coreboot/+/42193/3/src/soc/mediatek/mt8183/dra... PS3, Line 953: (0x3 << 4) | (0x1 << 7) | (0x1 << 13), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/42193/3/src/soc/mediatek/mt8183/dra... PS3, Line 953: (0x3 << 4) | (0x1 << 7) | (0x1 << 13), please, no spaces at the start of a line
Hello build bot (Jenkins), Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42193
to look at the new patch set (#4).
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
soc/mediatek/mt8183: Fix some programming errors of DRAMC setting
Fix some programming errors.
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui
Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 3 files changed, 58 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42193/4
Duan huayang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
Patch Set 4:
(6 comments)
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG@7 PS2, Line 7: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting
I’d prefer a more specific commit message summary. Maybe split the commit up.
this is found by code review.
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG@9 PS2, Line 9: Fix some programming errors.
Please elaborate.
this is found by code review.
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG@13 PS2, Line 13: TEST=Boots correctly on Kukui
… as before, right? […]
no error before, this is found by code review.
https://review.coreboot.org/c/coreboot/+/42193/2/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/42193/2/src/soc/mediatek/mt8183/dra... PS2, Line 894: (0x3 << 4) | (0x1 << 7) | (0x1 << 13),
Move to next line.
Done
https://review.coreboot.org/c/coreboot/+/42193/2/src/soc/mediatek/mt8183/dra... PS2, Line 952: (0x3 << 4) | (0x1 << 7) | (0x1 << 13),
Move to next line.
Done
https://review.coreboot.org/c/coreboot/+/42193/2/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/42193/2/src/soc/mediatek/mt8183/dra... PS2, Line 51: size_t
u8
Done
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG@7 PS2, Line 7: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting
this is found by code review.
Maybe something like
soc/mediatek/mt8183: Add missing register settings for channels
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG@9 PS2, Line 9: Fix some programming errors.
this is found by code review.
Also mention the typo fix.
Also fix a typo (0x1 < 0) to (0x1 << 0).
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG@13 PS2, Line 13: TEST=Boots correctly on Kukui
no error before, […]
Yes, kukui should boot as before.
https://review.coreboot.org/c/coreboot/+/42193/4/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/42193/4/src/soc/mediatek/mt8183/dra... PS4, Line 894: Please remove this extra tab. Better to put format changes in a separate CL.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
Patch Set 4: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42193/4/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/42193/4/src/soc/mediatek/mt8183/dra... PS4, Line 894:
Please remove this extra tab. Better to put format changes in a separate CL.
I think this was moved to the following line because of the increased line width, and was aligned with the values on the following line.
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42193/4/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/42193/4/src/soc/mediatek/mt8183/dra... PS4, Line 894:
I think this was moved to the following line because of the increased line width, and was aligned wi […]
Ooops, I didn't notice the register was changed. For indentation, I'd still suggest writing
clrsetbits32(&ch[0]..., (...) | (...), // one tab (...) | (...)); // one tab also
to be consistent with the code above (line 874-887).
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42193/4/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/42193/4/src/soc/mediatek/mt8183/dra... PS4, Line 894:
Ooops, I didn't notice the register was changed. For indentation, I'd still suggest writing […]
Sounds good.
Hello build bot (Jenkins), Angel Pons, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42193
to look at the new patch set (#5).
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
soc/mediatek/mt8183: Fix some programming errors of DRAMC setting
Fix some programming errors.
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui
Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 3 files changed, 58 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42193/5
Duan huayang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42193/4/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/42193/4/src/soc/mediatek/mt8183/dra... PS4, Line 894:
Please remove this extra tab. Better to put format changes in a separate CL.
Done
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
Patch Set 5:
(6 comments)
https://review.coreboot.org/c/coreboot/+/42193/5/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/42193/5/src/soc/mediatek/mt8183/dra... PS5, Line 893: clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], trailing whitespace
https://review.coreboot.org/c/coreboot/+/42193/5/src/soc/mediatek/mt8183/dra... PS5, Line 894: (0x3 << 4) | (0x1 << 7) | (0x1 << 13), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/42193/5/src/soc/mediatek/mt8183/dra... PS5, Line 894: (0x3 << 4) | (0x1 << 7) | (0x1 << 13), please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/42193/5/src/soc/mediatek/mt8183/dra... PS5, Line 952: clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], trailing whitespace
https://review.coreboot.org/c/coreboot/+/42193/5/src/soc/mediatek/mt8183/dra... PS5, Line 953: (0x3 << 4) | (0x1 << 7) | (0x1 << 13), code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/42193/5/src/soc/mediatek/mt8183/dra... PS5, Line 953: (0x3 << 4) | (0x1 << 7) | (0x1 << 13), please, no spaces at the start of a line
Hello build bot (Jenkins), Angel Pons, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42193
to look at the new patch set (#6).
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
soc/mediatek/mt8183: Fix some programming errors of DRAMC setting
Fix some programming errors.
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui
Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 3 files changed, 58 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42193/6
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG@7 PS2, Line 7: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting
Maybe something like […]
Huayang, could you change the commit message title to what I suggested?
https://review.coreboot.org/c/coreboot/+/42193/6/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/42193/6/src/soc/mediatek/mt8183/dra... PS6, Line 894: Remove this tab.
https://review.coreboot.org/c/coreboot/+/42193/6/src/soc/mediatek/mt8183/dra... PS6, Line 895: Remove this tab.
Hello build bot (Jenkins), Angel Pons, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42193
to look at the new patch set (#7).
Change subject: soc/mediatek/mt8183: Add missing register settings for channels ......................................................................
soc/mediatek/mt8183: Add missing register settings for channels
Some DRAM control settings need apply to all channels, add those missing settings.
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui
Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 3 files changed, 59 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42193/7
Duan huayang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Add missing register settings for channels ......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG@7 PS2, Line 7: soc/mediatek/mt8183: Fix some programming errors of DRAMC setting
Huayang, could you change the commit message title to what I suggested?
Done
https://review.coreboot.org/c/coreboot/+/42193/6/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/42193/6/src/soc/mediatek/mt8183/dra... PS6, Line 894:
Remove this tab.
Done
https://review.coreboot.org/c/coreboot/+/42193/6/src/soc/mediatek/mt8183/dra... PS6, Line 895:
Remove this tab.
Done
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Add missing register settings for channels ......................................................................
Patch Set 7:
(4 comments)
Almost done!
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42193/2//COMMIT_MSG@9 PS2, Line 9: Fix some programming errors.
Also mention the typo fix. […]
Left another comment.
https://review.coreboot.org/c/coreboot/+/42193/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42193/7//COMMIT_MSG@9 PS7, Line 9: add so add
https://review.coreboot.org/c/coreboot/+/42193/7//COMMIT_MSG@9 PS7, Line 9: need need to
https://review.coreboot.org/c/coreboot/+/42193/7//COMMIT_MSG@10 PS7, Line 10: missing settings. Please add
Also fix a typo (0x1 < 0) to (0x1 << 0).
Hello build bot (Jenkins), Angel Pons, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42193
to look at the new patch set (#8).
Change subject: soc/mediatek/mt8183: Add missing register settings for channels ......................................................................
soc/mediatek/mt8183: Add missing register settings for channels
Some DRAM control settings need to apply to all channels, so add those missing settings. Also fix a typo (0x1 < 0) to (0x << 0).
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui
Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 3 files changed, 59 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42193/8
Duan huayang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Add missing register settings for channels ......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/c/coreboot/+/42193/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42193/7//COMMIT_MSG@9 PS7, Line 9: add
so add
Done
https://review.coreboot.org/c/coreboot/+/42193/7//COMMIT_MSG@9 PS7, Line 9: need
need to
Done
https://review.coreboot.org/c/coreboot/+/42193/7//COMMIT_MSG@10 PS7, Line 10: missing settings.
Please add […]
Done
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Add missing register settings for channels ......................................................................
Patch Set 8: Code-Review+1
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Add missing register settings for channels ......................................................................
Patch Set 8: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Add missing register settings for channels ......................................................................
Patch Set 8: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/42193/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42193/8//COMMIT_MSG@11 PS8, Line 11: 0x nit: 0x1
Hello Hung-Te Lin, build bot (Jenkins), Angel Pons, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42193
to look at the new patch set (#9).
Change subject: soc/mediatek/mt8183: Add missing register settings for channels ......................................................................
soc/mediatek/mt8183: Add missing register settings for channels
Some DRAM control settings need to apply to all channels, so add those missing settings. Also fix a typo (0x1 < 0) to (0x1 << 0).
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui
Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 3 files changed, 59 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42193/9
Duan huayang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Add missing register settings for channels ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42193/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42193/8//COMMIT_MSG@11 PS8, Line 11: 0x
nit: 0x1
Done
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42193 )
Change subject: soc/mediatek/mt8183: Add missing register settings for channels ......................................................................
soc/mediatek/mt8183: Add missing register settings for channels
Some DRAM control settings need to apply to all channels, so add those missing settings. Also fix a typo (0x1 < 0) to (0x1 << 0).
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui
Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a Signed-off-by: Huayang Duan huayang.duan@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42193 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Yu-Ping Wu yupingso@google.com Reviewed-by: Hung-Te Lin hungte@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 3 files changed, 59 insertions(+), 35 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, but someone else must approve
diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 6f7ae377..9ae0aae 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -56,9 +56,9 @@ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { setbits32(&ch[chn].ao.dvfsdll, 0x1 << 5); setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 29); - clrsetbits32(&ch[0].ao.shuctrl2, 0x7f, dll_idle); + clrsetbits32(&ch[chn].ao.shuctrl2, 0x7f, dll_idle);
- setbits32(&ch[0].phy.misc_ctrl0, 0x3 << 19); + setbits32(&ch[chn].phy.misc_ctrl0, 0x3 << 19); setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24); setbits32(&ch[chn].ao.dvfsdll, 0x1 << 7); } @@ -889,12 +889,12 @@
clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x0 << 2) | (0x3 << 8)); - clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x4 << 20); - - clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), - (0x2 << 4) | (0x0 << 7) | (0x0 << 13)); - clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20); - clrbits32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13)); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x4 << 20); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], + (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + (0x2 << 4) | (0x0 << 7) | (0x0 << 13)); + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x4 << 20); + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 7) | (0x1 << 13));
for (size_t r = 0; r < 2; r++) { int value = ((r == 0) ? 0x1a : 0x26); @@ -948,11 +948,12 @@
clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x1 << 2) | (0x4 << 8)); - clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], + (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x1 << 4) | (0x1 << 7) | (0x1 << 13)); - clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&ch[0].phy.b[1].dq[7], + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 7) | (0x1 << 13), (0x1 << 7) | (0x1 << 13));
for (size_t r = 0; r < 2; r++) { @@ -1056,7 +1057,7 @@ clrsetbits32(&ch[0].phy.ca_cmd[6], (0x1 << 6) | (0x3 << 14) | (0x1 << 16), (0x0 << 6) | (0x0 << 14) | (0x0 << 16));
- clrbits32(&ch[0].phy.pll3, 0x1 < 0); + clrbits32(&ch[0].phy.pll3, 0x1 << 0); setbits32(&ch[0].phy.b[0].dq[3], 0x1 << 3); setbits32(&ch[0].phy.b[1].dq[3], 0x1 << 3);
@@ -1087,7 +1088,11 @@
for (size_t b = 0; b < 2; b++) setbits32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10)); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); setbits32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0); + setbits32(&ch[1].phy.shu[0].ca_dll[0], 0x1 << 0); + dramc_set_broadcast(DRAMC_BROADCAST_ON);
for (size_t b = 0; b < 2; b++) clrsetbits32(&ch[0].phy.shu[0].b[b].dll[0], diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index aa156f7..4a884b1 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -47,10 +47,12 @@ broadcast_bak = dramc_get_broadcast(); dramc_set_broadcast(DRAMC_BROADCAST_OFF);
- clrbits32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); - write32(&ch[0].phy.misc_spm_ctrl2, 0x0); - write32(&ch[0].phy.misc_spm_ctrl0, 0x0); - clrbits32(&ch[0].ao.impcal, 0x1 << 31); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + clrbits32(&ch[chn].phy.misc_spm_ctrl1, 0xf << 0); + write32(&ch[chn].phy.misc_spm_ctrl2, 0x0); + write32(&ch[chn].phy.misc_spm_ctrl0, 0x0); + clrbits32(&ch[chn].ao.impcal, 0x1 << 31); + }
impcal_bak = read32(&ch[0].ao.impcal); dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVP); @@ -91,7 +93,7 @@ if (term == ODT_ON) setbits32(&ch[0].ao.impcal, 0x1 << 21); clrsetbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11, - DRVP_result << 4 | 0x1f << 11); + DRVP_result << 4); clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3);
for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) { @@ -150,9 +152,6 @@ sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2]; sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3];
- clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3); - dramc_sw_imp_cal_vref_sel(dq_term, IMPCAL_STAGE_DRVP); - /* DQ */ clrsetbits32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0), (sw_impedance[dq_term][0] << 5) | @@ -202,7 +201,10 @@ SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[0], SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 0);
+ dramc_set_broadcast(DRAMC_BROADCAST_OFF); clrsetbits32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); + clrsetbits32(&ch[1].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); + dramc_set_broadcast(DRAMC_BROADCAST_ON); }
static void transfer_pll_to_spm_control(void) diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index aac6d17..ee9b9b6 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -365,12 +365,30 @@ clrsetbits32(&ch[chn].ao.stbcal, 0x1 << 22, (on ? 0x1 : 0) << 22); }
-static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn) +static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn, u8 freq_group) { + u8 dvs_delay; + struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[0];
- clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, 0x3 << 20); + switch (freq_group) { + case LP4X_DDR1600: + dvs_delay = 5; + break; + case LP4X_DDR2400: + dvs_delay = 4; + break; + case LP4X_DDR3200: + case LP4X_DDR3600: + dvs_delay = 3; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, dvs_delay << 20); + clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, dvs_delay << 20); clrbits32(&shu->b[0].dq[7], (0x1 << 12) | (0x1 << 13)); clrbits32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13)); } @@ -408,7 +426,13 @@ dramc_hw_gating_onoff(chn, false); clrbits32(&ch[chn].ao.stbcal2, 0x1 << 28);
- setbits32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11)); + for (size_t r = 0; r < 2; r++) { + for (size_t b = 0; b < 2; b++) + clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2], + (0x1 << 28) | (0x1 << 23) | (0x3 << 30)); + clrbits32(&ch[chn].phy.r0_ca_rxdvs[2], 0x3 << 30); + } + setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 7); clrbits32(&ch[chn].ao.refctrl0, 0x1 << 18); clrbits32(&ch[chn].ao.mrs, 0x3 << 24); setbits32(&ch[chn].ao.mpc_option, 0x1 << 17); @@ -416,21 +440,14 @@ clrsetbits32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0); clrsetbits32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0);
- dramc_rx_input_delay_tracking_init_by_freq(chn); + dramc_rx_input_delay_tracking_init_by_freq(chn, freq_group);
setbits32(&ch[chn].ao.dummy_rd, 0x1 << 25); setbits32(&ch[chn].ao.drsctrl, 0x1 << 0); if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) - clrbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); + clrbits32(&ch[chn].ao.shu[0].drving[0], 0x1 << 31); else - setbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); - } - - for (size_t r = 0; r < 2; r++) { - for (size_t b = 0; b < 2; b++) - clrbits32(&ch[0].phy.r[r].b[b].rxdvs[2], - (0x1 << 28) | (0x1 << 23) | (0x3 << 30)); - clrbits32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30); + setbits32(&ch[chn].ao.shu[0].drving[0], 0x1 << 31); } }
-
Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
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Duan huayang (Code Review)
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Hung-Te Lin (Code Review)
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Paul Menzel (Code Review)
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Yu-Ping Wu (Code Review)