Change in coreboot[master]: soc/amd/cezanne: add MP init and SMM initialization

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50505 )

Change subject: soc/amd/cezanne: add MP init and SMM initialization
......................................................................

soc/amd/cezanne: add MP init and SMM initialization

Change-Id: I38d52394b5f6ffb837fa753fc9e82c0450c6aae3
Signed-off-by: Felix Held 
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/cpu.c
2 files changed, 46 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/50505/1

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 88f609b..da33754 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -21,6 +21,8 @@
    select HAVE_SMI_HANDLER
    select IDT_IN_EVERY_STAGE
    select IOAPIC
+	select PARALLEL_MP
+	select PARALLEL_MP_AP_WORK
    select PLATFORM_USES_FSP2_0
    select RESET_VECTOR_IN_RAM
    select SOC_AMD_COMMON
@@ -42,6 +44,7 @@
    select SUPPORT_CPU_UCODE_IN_CBFS
    select UDK_2017_BINDING
    select X86_AMD_FIXED_MTRRS
+	select X86_AMD_INIT_SIPI

config CHIPSET_DEVICETREE
    string
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index b199d99..cfe0f8c 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -1,14 +1,57 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <amdblocks/cpu.h>
+#include <amdblocks/smm.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/lapic.h>
+#include <cpu/x86/mp.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <soc/cpu.h>
+#include <soc/iomap.h>
+#include <soc/reset.h>
+
+/* MP and SMM loading initialization */
+
+/*
+ * Do essential initialization tasks before APs can be fired up -
+ *
+ *  1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
+ *  creates the MTRR solution that the APs will use. Otherwise APs will try to
+ *  apply the incomplete solution as the BSP is calculating it.
+ */
+static void pre_mp_init(void)
+{
+	x86_setup_mtrrs_with_detect_no_above_4gb();
+	x86_mtrr_check();
+}
+
+static void post_mp_init(void)
+{
+	global_smi_enable();
+	apm_control(APM_CNT_SMMINFO);
+}
+
+static const struct mp_ops mp_ops = {
+	.pre_mp_init = pre_mp_init,
+	.get_cpu_count = get_cpu_count,
+	.get_smm_info = get_smm_info,
+	.relocation_handler = smm_relocation_handler,
+	.post_mp_init = post_mp_init,
+};

void mp_init_cpus(struct bus *cpu_bus)
 {
+	/* Clear for take-off */
+	if (mp_init_with_smm(cpu_bus, &mp_ops) < 0)
+		printk(BIOS_ERR, "MP initialization failure.\n");
+
+	/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
+	mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+
+	set_warm_reset_flag();
 }

static void zen_2_3_init(struct device *dev)