Change in coreboot[master]: sc7280: Add PCIe host controller driver

[Michael Niewöhner (Code Review)]

Attention is currently required from: Ravi Kumar Bokka, Furquan Shaikh, Julius Werner, Prasad Malisetty, mturney mturney.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53902 )

Change subject: sc7280: Add PCIe host controller driver
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Patch Set 84: Code-Review-1

(4 comments)

File src/soc/qualcomm/sc7280/include/soc/pcie.h:

https://review.coreboot.org/c/coreboot/+/53902/comment/d1569719_3889c02e 
PS84, Line 186: 	(((d) >> 8) & 0x7)
              : #define PCIE_SLOT(devfn)	(((devfn) >> 3) & 0x1f)
              : #define PCIE_MASK_BUS(bdf)	((bdf) & 0xffff)
              : #define PCIE_ADD_BUS(bus, devfn)	(((bus) << 16) | (devfn))
              : #define PCIE_BUS(d)		(((d) >> 16) & 0xff)
              : #define PCIE_BDF(b, d, f)	((b) << 16 | (d) << 11 | (f) << 8)
              : #define PCIE_VENDEV(v, d)	(((v) << 16) | (d))
              : #define PCIE_ANY_ID		(~0)
align

https://review.coreboot.org/c/coreboot/+/53902/comment/a2c51260_97585ae7 
PS84, Line 181: define PCIE_DEVFN(slot, func)	((((slot) & 0x1f) << 3) | ((func) & 0x07))
              : 
              : #define PCIE_DEV(_bus, _dev, _fn) {(0x80000000 | \
              : 	(uint32_t)(_bus << 16) | (uint32_t)(_dev << 11) | (uint32_t)(_fn << 8))}
              : 
              : #define PCIE_FUNC(d)		(((d) >> 8) & 0x7)
              : #define PCIE_SLOT(devfn)	(((devfn) >> 3) & 0x1f)
              : #define PCIE_MASK_BUS(bdf)	((bdf) & 0xffff)
              : #define PCIE_ADD_BUS(bus, devfn)	(((bus) << 16) | (devfn))
              : #define PCIE_BUS(d)		(((d) >> 16) & 0xff)
              : #define PCIE_BDF(b, d, f)	((b) << 16 | (d) << 11 | (f) << 8)
              : #define PCIE_VENDEV(v, d)	(((v) << 16) | (d))
              : #define PCIE_ANY_ID		(~0)
don't reinvent the wheel, please. make use of existing coreboot code where possible. this is not the only occurence

File src/soc/qualcomm/sc7280/include/soc/qcom_qmp_phy.h:

https://review.coreboot.org/c/coreboot/+/53902/comment/5fb841dc_effb3e3b 
PS84, Line 68: #define QSERDES_V4_TX_PI_QEC_CTRL		0x104
align

https://review.coreboot.org/c/coreboot/+/53902/comment/92ed8512_40e72705 
PS84, Line 83: #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE			0x060
align