Change in coreboot[master]: mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63295 )

Change subject: mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device
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mb/google/skyrim/var/baseboard: Set Clk request for WLAN/SD/SSD device

Setting the clock source depends on clock request pin for WLAN/SD/SSD
device. Also turn off the unused (CLKREQ#3) clock sources.In skyrim,
clock source 0/1/2 are routed for WLAN/SD/SSD device.

BUG=b:227297986
BRANCH=none
TEST=Build

Signed-off-by: Chris.Wang 
Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63295
Tested-by: build bot (Jenkins) 
Reviewed-by: Jon Murphy 
Reviewed-by: Felix Held 
---
M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved
  Jon Murphy: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
index 7f74d6d..a6894ee 100644
--- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
@@ -47,6 +47,12 @@
    register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # Audio/SAR
    register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC

+	# general purpose PCIe clock output configuration
+	register "gpp_clk_config[0]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[1]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[2]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[3]" = "GPP_CLK_OFF"
+
    register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works

device domain 0 on

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.