Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39195 )

Change subject: mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
......................................................................

mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP

Add memory initialization parameters for Jasper Lake RVP boards
Jasper Lake RVP supports two variants, one with memory LPDDR4
and another with DDR4
Based on board id, mainboard will pass correct memory parameters
to the fsp.

BUG=None
BRANCH=None
TEST=Check compilation for Jasper Lake RVP and check memory training passes.

Change-Id: Idc92363a2148990df16c2068c7986013d015f604
Signed-off-by: Ronak Kanabar 
Signed-off-by: Maulik V Vaghela 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39195
Reviewed-by: Aamir Bohra 
Reviewed-by: V Sowmya 
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/jasperlake_rvp/board_id.c
M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c
M src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc
A src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex
M src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc
A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c
7 files changed, 197 insertions(+), 10 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Aamir Bohra: Looks good to me, approved
  V Sowmya: Looks good to me, approved

diff --git a/src/mainboard/intel/jasperlake_rvp/board_id.c b/src/mainboard/intel/jasperlake_rvp/board_id.c
index 1913d3f..09d73cb 100644
--- a/src/mainboard/intel/jasperlake_rvp/board_id.c
+++ b/src/mainboard/intel/jasperlake_rvp/board_id.c
@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright 2020 The coreboot project Authors
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -29,7 +30,10 @@
    return id;
 }

-/* Get Board ID via EC I/O port write/read */
+/*
+ * Get Board ID via EC I/O port write/read
+ * Board id is 5 bit, so mask other bits while returning board id.
+ */
 int get_board_id(void)
 {
    MAYBE_STATIC_NONZERO int id = -1;
@@ -47,5 +51,6 @@
    		}
    	}
    }
-	return id;
+
+	return (id & 0x1f);
 }
diff --git a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c
index b072a90..8858e44 100644
--- a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c
@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright 2020 The coreboot project Authors
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -11,11 +12,36 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-
-#include <fsp/api.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <soc/meminit_jsl.h>
 #include <soc/romstage.h>
+#include "board_id.h"

-void mainboard_memory_init_params(FSPM_UPD *mupd)
+void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
-	/* ToDo : Fill FSP-M memory params */
+	static struct spd_info jslrvp_spd_info;
+	uint8_t board_id = get_board_id();
+	const struct mb_cfg *board_cfg = variant_memcfg_config(board_id);
+
+	/* TODO: Read the resistor strap to get number of memory segments */
+	bool half_populated = false;
+
+	/* Check board id and fill correct parameters to upd */
+	if (board_id == jsl_ddr4) {
+		/* Initialize spd information for DDR4 board */
+		jslrvp_spd_info.read_type = READ_SMBUS;
+		jslrvp_spd_info.spd_spec.spd_smbus_address[0] = 0xA0;
+		jslrvp_spd_info.spd_spec.spd_smbus_address[1] = 0xA2;
+		jslrvp_spd_info.spd_spec.spd_smbus_address[2] = 0xA4;
+		jslrvp_spd_info.spd_spec.spd_smbus_address[3] = 0xA6;
+
+	} else if (board_id == jsl_lpddr4) {
+		/* Initialize spd information for LPDDR4 board */
+		jslrvp_spd_info.read_type = READ_SPD_CBFS;
+		jslrvp_spd_info.spd_spec.spd_index = 0x00;
+	}
+
+	/* Initialize variant specific configurations */
+	memcfg_init(&memupd->FspmConfig, board_cfg, &jslrvp_spd_info, half_populated);
 }
diff --git a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc
index 4cde260..2909281 100644
--- a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc
+++ b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc
@@ -12,8 +12,6 @@
 ## GNU General Public License for more details.
 ##

-romstage-y += spd_util.c
-
 SPD_BIN = $(obj)/spd.bin

-SPD_SOURCES = empty	# 0b000
+SPD_SOURCES = jslrvp	# 0b000
diff --git a/src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex b/src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex
new file mode 100644
index 0000000..a27c249
--- /dev/null
+++ b/src/mainboard/intel/jasperlake_rvp/spd/jslrvp.spd.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 15 21 B0 08 00 40 00 00 0A 22 00 00
+00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
[phone] 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h
index 6beef66..27c645b 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/variants.h
@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright 2020 The coreboot project Authors
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -16,14 +17,21 @@
 #define __BASEBOARD_VARIANTS_H__

#include <soc/gpio.h>
+#include <soc/meminit_jsl.h>
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>

+enum jsl_board_id {
+	jsl_ddr4 = 1,
+	jsl_lpddr4 = 4,
+};
+
 /* The next set of functions return the gpio table and fill in the number of
  * entries for each table. */

const struct pad_config *variant_gpio_table(size_t *num);
 const struct pad_config *variant_early_gpio_table(size_t *num);
 const struct cros_gpio *variant_cros_gpios(size_t *num);
+const struct mb_cfg *variant_memcfg_config(uint8_t board_id);

#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc
index 9d44bb0..885a172 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc
@@ -13,5 +13,5 @@
 ##

bootblock-y += gpio.c
-
+romstage-y += memory.c
 ramstage-y += gpio.c
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c
new file mode 100644
index 0000000..1915a1e
--- /dev/null
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <baseboard/gpio.h>
+#include <gpio.h>
+#include <soc/meminit_jsl.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg jslrvp_ddr4_memcfg_cfg = {
+
+	.dq_map[DDR_CH0] = {
+		{0xf, 0xf0},
+		{0xf, 0xf0},
+		{0xff, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0}
+	},
+
+	.dq_map[DDR_CH1] = {
+		{0xf, 0xf0},
+		{0xf, 0xf0},
+		{0xff, 0x0},
+		{0x0, 0x0},
+		{0x00, 0x0},
+		{0x00, 0x0}
+	},
+
+	/*
+	 * The dqs_map arrays map the ddr4 pins to the SoC pins
+	 * for both channels.
+	 *
+	 * the index = pin number on ddr4 part
+	 * the value = pin number on SoC
+	 */
+	.dqs_map[DDR_CH0] = {0, 1, 3, 2, 4, 5, 6, 7},
+	.dqs_map[DDR_CH1] = {1, 0, 4, 5, 2, 3, 6, 7},
+
+	/* Baseboard uses 100, 100 and 100 rcomp resistors */
+	.rcomp_resistor = {100, 100, 100},
+
+	/* Baseboard Rcomp target values */
+	.rcomp_targets = {0, 0, 0, 0, 0},
+
+	/* Disable Early Command Training */
+	.ect = 1,
+
+	/* Set Board Type */
+	.UserBd = BOARD_TYPE_MOBILE,
+};
+
+static const struct mb_cfg jslrvp_lpddr4_memcfg_cfg = {
+
+	.dq_map[DDR_CH0] = {
+		{0xf, 0xf0},
+		{0xf, 0xf0},
+		{0xff, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0},
+		{0x0, 0x0}
+	},
+
+	.dq_map[DDR_CH1] = {
+		{0xf, 0xf0},
+		{0xf, 0xf0},
+		{0xff, 0x0},
+		{0x0, 0x0},
+		{0x00, 0x0},
+		{0x00, 0x0}
+	},
+
+	/*
+	 * The dqs_map arrays map the ddr4 pins to the SoC pins
+	 * for both channels.
+	 *
+	 * the index = pin number on ddr4 part
+	 * the value = pin number on SoC
+	 */
+	.dqs_map[DDR_CH0] = {0, 3, 2, 1, 7, 5, 4, 6},
+	.dqs_map[DDR_CH1] = {3, 1, 2, 0, 4, 7, 6, 5},
+
+	/* Baseboard uses 100, 100 and 100 rcomp resistors */
+	.rcomp_resistor = {100, 100, 100},
+
+	/*
+	 * Baseboard Rcomp target values.
+	 */
+	.rcomp_targets = {80, 40, 40, 40, 30},
+
+	/* Disable Early Command Training */
+	.ect = 1,
+
+	/* Set Board Type */
+	.UserBd = BOARD_TYPE_ULT_ULX,
+};
+
+const struct mb_cfg *variant_memcfg_config(uint8_t board_id)
+{
+	if (board_id == jsl_ddr4)
+		return &jslrvp_ddr4_memcfg_cfg;
+	else if (board_id == jsl_lpddr4)
+		return &jslrvp_lpddr4_memcfg_cfg;
+
+	die("unsupported board id : 0x%x\n", board_id);
+}