HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39028 )
Change subject: soc/rockchip: Fix typos ......................................................................
soc/rockchip: Fix typos
Change-Id: I85ccb9e1458340bd5bc2a0eb9abed8d0eeb2fe65 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/rockchip/common/edp.c M src/soc/rockchip/rk3288/hdmi.c M src/soc/rockchip/rk3288/tsadc.c M src/soc/rockchip/rk3399/clock.c M src/soc/rockchip/rk3399/mipi.c M src/soc/rockchip/rk3399/tsadc.c 6 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/39028/1
diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index 18afc3a..060099c 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -135,7 +135,7 @@
static void rk_edp_init_aux(struct rk_edp *edp) { - /* Clear inerrupts related to AUX channel */ + /* Clear interrupts related to AUX channel */ write32(&edp->regs->dp_int_sta, AUX_FUNC_EN_N);
/* Disable AUX channel module */ diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index cd9890b..3b8c77d 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -733,7 +733,7 @@ u32 trytime = 5; u32 n, j, val;
- /* set ddc i2c clk which devided from ddc_clk to 100khz */ + /* set ddc i2c clk which divided from ddc_clk to 100kHz */ write32(&hdmi_regs->i2cm_ss_scl_hcnt_0_addr, 0x7a); write32(&hdmi_regs->i2cm_ss_scl_lcnt_0_addr, 0x8d); clrsetbits32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE, diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index de3d058..7a1e34d 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -100,7 +100,7 @@
/* tsadc iomux must be set after the tshut polarity setting, - since the tshut polarity defalut low active, + since the tshut polarity default low active, so if you enable tsadc iomux,it will output high */ setbits32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT); diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 4cd2839..d2f5b7c 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -304,7 +304,7 @@ u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
printk(BIOS_DEBUG, "PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " - "postdiv2=%d, vco=%u khz, output=%u khz\n", + "postdiv2=%d, vco=%u kHz, output=%u kHz\n", pll_con, div->fbdiv, div->refdiv, div->postdiv1, div->postdiv2, vco_khz, output_khz); assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && @@ -485,7 +485,7 @@
/* some cru registers changed by bootrom, we'd better reset them to * reset/default values described in TRM to avoid confusion in kernel. - * Please consider these threee lines as a fix of bootrom bug. + * Please consider these three lines as a fix of bootrom bug. */ write32(&cru_ptr->clksel_con[12], 0xffff4101); write32(&cru_ptr->clksel_con[19], 0xffff033f); diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index 751c8a5..5df5fdf 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -319,7 +319,7 @@ min_prediv = DIV_ROUND_UP(fref, 40 * MHz); max_prediv = fref / (5 * MHz);
- /* constraint: 80MHz <= Fvco <= 1500Mhz */ + /* constraint: 80MHz <= Fvco <= 1500MHz */ fvco_min = 80 * MHz; fvco_max = 1500 * MHz; min_delta = 1500 * MHz; diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c index 1cdb355..9f69915 100644 --- a/src/soc/rockchip/rk3399/tsadc.c +++ b/src/soc/rockchip/rk3399/tsadc.c @@ -112,7 +112,7 @@
/* setup the automatic mode: * AUTO_PERIOD: interleave between every two accessing of TSADC - * AUTO_DEBOUNCE: only generate interrupt or TSHUT when temprature + * AUTO_DEBOUNCE: only generate interrupt or TSHUT when temperature * is higher than COMP_INT for "debounce" times * AUTO_PERIOD_HT: the interleave between every two accessing after the * temperature is higher than COMP_SHUT or COMP_INT @@ -123,7 +123,7 @@ write32(&rk3399_tsadc->hight_int_debounce, AUTO_DEBOUNCE); write32(&rk3399_tsadc->auto_period_ht, AUTO_PERIOD_HT); write32(&rk3399_tsadc->hight_tshut_debounce, AUTO_DEBOUNCE_HT); - /* Enable the src0, negative temprature coefficient */ + /* Enable the src0, negative temperature coefficient */ setbits32(&rk3399_tsadc->auto_con, Q_SEL | SRC0_EN); udelay(100); setbits32(&rk3399_tsadc->auto_con, AUTO_EN);
Hello Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39028
to look at the new patch set (#2).
Change subject: soc/rockchip: Fix typos ......................................................................
soc/rockchip: Fix typos
Change-Id: I85ccb9e1458340bd5bc2a0eb9abed8d0eeb2fe65 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/rockchip/common/edp.c M src/soc/rockchip/rk3288/hdmi.c M src/soc/rockchip/rk3288/tsadc.c M src/soc/rockchip/rk3399/clock.c M src/soc/rockchip/rk3399/mipi.c M src/soc/rockchip/rk3399/tsadc.c 6 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/39028/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39028 )
Change subject: soc/rockchip: Fix typos ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39028/2/src/soc/rockchip/rk3288/hdm... File src/soc/rockchip/rk3288/hdmi.c:
https://review.coreboot.org/c/coreboot/+/39028/2/src/soc/rockchip/rk3288/hdm... PS2, Line 736: devided divided?
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39028 )
Change subject: soc/rockchip: Fix typos ......................................................................
Patch Set 2:
(1 comment)
Thx
https://review.coreboot.org/c/coreboot/+/39028/2/src/soc/rockchip/rk3288/hdm... File src/soc/rockchip/rk3288/hdmi.c:
https://review.coreboot.org/c/coreboot/+/39028/2/src/soc/rockchip/rk3288/hdm... PS2, Line 736: devided
divided?
divided from ... to ?
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39028 )
Change subject: soc/rockchip: Fix typos ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/39028/2/src/soc/rockchip/rk3288/hdm... File src/soc/rockchip/rk3288/hdmi.c:
https://review.coreboot.org/c/coreboot/+/39028/2/src/soc/rockchip/rk3288/hdm... PS2, Line 736: devided
divided from ... […]
There's probably a clock divisor in there somewhere, but it's also derived, and with from ... to, derived seems to make more sense (to me).
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39028 )
Change subject: soc/rockchip: Fix typos ......................................................................
soc/rockchip: Fix typos
Change-Id: I85ccb9e1458340bd5bc2a0eb9abed8d0eeb2fe65 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/39028 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/soc/rockchip/common/edp.c M src/soc/rockchip/rk3288/hdmi.c M src/soc/rockchip/rk3288/tsadc.c M src/soc/rockchip/rk3399/clock.c M src/soc/rockchip/rk3399/mipi.c M src/soc/rockchip/rk3399/tsadc.c 6 files changed, 8 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index 18afc3a..060099c 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -135,7 +135,7 @@
static void rk_edp_init_aux(struct rk_edp *edp) { - /* Clear inerrupts related to AUX channel */ + /* Clear interrupts related to AUX channel */ write32(&edp->regs->dp_int_sta, AUX_FUNC_EN_N);
/* Disable AUX channel module */ diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index cd9890b..36a08a9 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -733,7 +733,7 @@ u32 trytime = 5; u32 n, j, val;
- /* set ddc i2c clk which devided from ddc_clk to 100khz */ + /* set ddc i2c clk which derived from ddc_clk to 100kHz */ write32(&hdmi_regs->i2cm_ss_scl_hcnt_0_addr, 0x7a); write32(&hdmi_regs->i2cm_ss_scl_lcnt_0_addr, 0x8d); clrsetbits32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE, diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index de3d058..7a1e34d 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -100,7 +100,7 @@
/* tsadc iomux must be set after the tshut polarity setting, - since the tshut polarity defalut low active, + since the tshut polarity default low active, so if you enable tsadc iomux,it will output high */ setbits32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT); diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 4cd2839..d2f5b7c 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -304,7 +304,7 @@ u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
printk(BIOS_DEBUG, "PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " - "postdiv2=%d, vco=%u khz, output=%u khz\n", + "postdiv2=%d, vco=%u kHz, output=%u kHz\n", pll_con, div->fbdiv, div->refdiv, div->postdiv1, div->postdiv2, vco_khz, output_khz); assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && @@ -485,7 +485,7 @@
/* some cru registers changed by bootrom, we'd better reset them to * reset/default values described in TRM to avoid confusion in kernel. - * Please consider these threee lines as a fix of bootrom bug. + * Please consider these three lines as a fix of bootrom bug. */ write32(&cru_ptr->clksel_con[12], 0xffff4101); write32(&cru_ptr->clksel_con[19], 0xffff033f); diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index 751c8a5..5df5fdf 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -319,7 +319,7 @@ min_prediv = DIV_ROUND_UP(fref, 40 * MHz); max_prediv = fref / (5 * MHz);
- /* constraint: 80MHz <= Fvco <= 1500Mhz */ + /* constraint: 80MHz <= Fvco <= 1500MHz */ fvco_min = 80 * MHz; fvco_max = 1500 * MHz; min_delta = 1500 * MHz; diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c index 1cdb355..9f69915 100644 --- a/src/soc/rockchip/rk3399/tsadc.c +++ b/src/soc/rockchip/rk3399/tsadc.c @@ -112,7 +112,7 @@
/* setup the automatic mode: * AUTO_PERIOD: interleave between every two accessing of TSADC - * AUTO_DEBOUNCE: only generate interrupt or TSHUT when temprature + * AUTO_DEBOUNCE: only generate interrupt or TSHUT when temperature * is higher than COMP_INT for "debounce" times * AUTO_PERIOD_HT: the interleave between every two accessing after the * temperature is higher than COMP_SHUT or COMP_INT @@ -123,7 +123,7 @@ write32(&rk3399_tsadc->hight_int_debounce, AUTO_DEBOUNCE); write32(&rk3399_tsadc->auto_period_ht, AUTO_PERIOD_HT); write32(&rk3399_tsadc->hight_tshut_debounce, AUTO_DEBOUNCE_HT); - /* Enable the src0, negative temprature coefficient */ + /* Enable the src0, negative temperature coefficient */ setbits32(&rk3399_tsadc->auto_con, Q_SEL | SRC0_EN); udelay(100); setbits32(&rk3399_tsadc->auto_con, AUTO_EN);
-
HAOUAS Elyes (Code Review) -
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)