[S] Change in coreboot[main]: soc/intel/xeon_sp: Create SSDT for Gen6 LPC controller

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84842?usp=email )

Change subject: soc/intel/xeon_sp: Create SSDT for Gen6 LPC controller
......................................................................

soc/intel/xeon_sp: Create SSDT for Gen6 LPC controller

In coreboot, LPC ACPI objects with its attached devices are
usually provided by static DSDT. For Xeon-SP Gen6 LPC, its logical
attached devices are created from dynamic SSDT (e.g. super IO).
Create a simple SSDT for LPC in dynamic way as well to complete
the device relationship chain.

Fix below issues during Linux OS boot. The issue will block
Windows OS boot as well.

[   22.986142] ACPI BIOS Error (bug): Could not resolve symbol [_SB.DI00.LPCB], AE_NOT_FOUND (20230628/dswload2-162)
[   22.986792] ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220)
[   22.987786] ACPI: Skipping parse of AML opcode: Scope (0x0010)

Change-Id: I08543fc77f0f3e633b05889e921c5183e6e20d8e
Signed-off-by: Lu, Pen-ChunX 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84842
Reviewed-by: Martin L Roth 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/common/block/include/intelblocks/lpc_lib.h
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/xeon_sp/lpc_gen6.c
3 files changed, 37 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Martin L Roth: Looks good to me, approved

diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index 0c4780b..bb28fc3 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -53,6 +53,9 @@
 /* Init SoC Specific LPC features. Common definition will be weak and
 each soc will need to define the init. */
 void lpc_soc_init(struct device *dev);
+/* Create SoC specific SSDT, by default it does nothing so that static
+DSDT could be used. */
+void lpc_soc_fill_ssdt(const struct device *dev);
 /* Fill up LPC IO resource structure inside SoC directory */
 void pch_lpc_soc_fill_io_resources(struct device *dev);
 /* Set LPC BIOS Control BILD bit. */
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index b05ee59..db06db9 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -16,6 +16,15 @@
    /* no-op */
 }

+/* Create SoC specific SSDT */
+__weak void lpc_soc_fill_ssdt(const struct device *dev)
+{
+	/*
+	 * no-op
+	 * by default it does nothing so that static DSDT could be used
+	 */
+}
+
 /* Fill up LPC IO resource structure inside SoC directory */
 __weak void pch_lpc_soc_fill_io_resources(struct device *dev)
 {
@@ -134,6 +143,7 @@
 #if CONFIG(HAVE_ACPI_TABLES)
    .write_acpi_tables	= southbridge_write_acpi_tables,
    .acpi_name		= lpc_acpi_name,
+	.acpi_fill_ssdt	        = lpc_soc_fill_ssdt,
 #endif
    .init			= lpc_soc_init,
    .scan_bus		= scan_static_bus,
diff --git a/src/soc/intel/xeon_sp/lpc_gen6.c b/src/soc/intel/xeon_sp/lpc_gen6.c
index d2aaec1..d4045a8 100644
--- a/src/soc/intel/xeon_sp/lpc_gen6.c
+++ b/src/soc/intel/xeon_sp/lpc_gen6.c
@@ -6,6 +6,30 @@
 #include <intelblocks/pcr.h>
 #include <soc/pcr_ids.h>

+#include <acpi/acpigen.h>
+#include <acpi/acpigen_pci.h>
+
+void lpc_soc_fill_ssdt(const struct device *dev)
+{
+	const char *scope = acpi_device_scope(dev);
+	const char *name = acpi_device_name(dev);
+
+	if (!scope || !name) {
+		printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", dev_path(dev));
+		return;
+	}
+
+	/* Device */
+	acpigen_write_scope(scope);
+	acpigen_write_device(name);
+
+	printk(BIOS_DEBUG, "%s.%s: %s\n", scope, name, dev_path(dev));
+	acpigen_write_ADR_pci_device(dev);
+
+	acpigen_write_device_end(); /* Device */
+	acpigen_write_scope_end(); /* Scope */
+}
+
 void lpc_soc_init(struct device *dev)
 {
    printk(BIOS_SPEW, "pch: lpc_init\n");