Change in coreboot[master]: soc/intel/skylake: Move SPI lock down config after PCI enumeration

[Barnali Sarkar (Code Review)]

Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/21064

Change subject: soc/intel/skylake: Move SPI lock down config after PCI enumeration
......................................................................

soc/intel/skylake: Move SPI lock down config after PCI enumeration

This patch to ensures that coreboot is meeting Intel Silicon
recommendation to performing register lockdown.

TEST=Ensure SPIBAR+HSFSTS(0x04) register FLOCKDN bit and WRSDIS
bit is set. Also, Bits 8-12 of SPIBAR+DLOCK(0x0C) register is set.

Change-Id: I8f5a952656e51d3bf365917b90d3056b46f899c5
Signed-off-by: Barnali Sarkar 
---
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/lockdown.c
2 files changed, 38 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/21064/1

diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index aed7e87..42d67ec 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -21,7 +21,6 @@
 #include <console/post_codes.h>
 #include <cpu/x86/smm.h>
 #include <device/pci.h>
-#include <intelblocks/fast_spi.h>
 #include <intelblocks/pcr.h>
 #include <reg_script.h>
 #include <spi-generic.h>
@@ -90,12 +89,6 @@
    config_t *config;
    u8 reg8;

-	/* Set FAST_SPI opcode menu */
-	fast_spi_set_opcode_menu();
-
-	/* Lock FAST_SPIBAR */
-	fast_spi_lock_bar();
-
    /* Display me status before we hide it */
    intel_me_status();

@@ -142,18 +135,6 @@
    	reg8 |= SMI_LOCK;
    	pci_write_config8(dev, GEN_PMCON_A, reg8);
    }
-
-	/* Bios Interface Lock */
-	if (config->LockDownConfigBiosInterface == 0)
-		fast_spi_set_bios_interface_lock_down();
-
-	/* Bios Lock */
-	if (config->LockDownConfigBiosLock == 0)
-		fast_spi_set_lock_enable();
-
-	/* SPIEiss */
-	if (config->LockDownConfigSpiEiss == 0)
-		fast_spi_set_eiss();
 }

static void soc_finalize(void *unused)
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
index e31cf09..cddb87b 100644
--- a/src/soc/intel/skylake/lockdown.c
+++ b/src/soc/intel/skylake/lockdown.c
@@ -17,6 +17,7 @@
 #include <bootstate.h>
 #include <chip.h>
 #include <console/console.h>
+#include <intelblocks/fast_spi.h>
 #include <intelblocks/pcr.h>
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
@@ -79,6 +80,40 @@
    pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
 }

+static void spi_lockdown_config(void)
+{
+	static struct soc_intel_skylake_config *config;
+	struct device *dev;
+
+	/* Set FAST_SPI opcode menu */
+	fast_spi_set_opcode_menu();
+
+	/* Discrete Lock Flash PR registers */
+	fast_spi_pr_dlock();
+
+	/* Lock FAST_SPIBAR */
+	fast_spi_lock_bar();
+
+	dev = PCH_DEV_SPI;
+	/* Check if SPI is enabled, else return */
+	if (dev == NULL || dev->chip_info == NULL)
+		return;
+
+	config = dev->chip_info;
+
+	/* Bios Interface Lock */
+	if (config->LockDownConfigBiosInterface == 0)
+		fast_spi_set_bios_interface_lock_down();
+
+	/* Bios Lock */
+	if (config->LockDownConfigBiosLock == 0)
+		fast_spi_set_lock_enable();
+
+	/* SPIEiss */
+	if (config->LockDownConfigSpiEiss == 0)
+		fast_spi_set_eiss();
+}
+
 static void platform_lockdown_config(void *unused)
 {
    /* LPC lock down configuration */
@@ -89,6 +124,9 @@

/* DMI lock down configuration */
    dmi_lockdown_config();
+
+	/* SPI lock down configuration */
+	spi_lockdown_config();
 }

BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,