[XS] Change in coreboot[main]: soc/amd/cezanne: Give PSP verstage 4K more space

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Yu-Ping Wu.

Karthik Ramasubramanian has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/83564?usp=email )

Change subject: soc/amd/cezanne: Give PSP verstage 4K more space
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Patch Set 2:

(1 comment)

File src/soc/amd/cezanne/include/soc/psp_verstage_addr.h:

https://review.coreboot.org/c/coreboot/+/83564/comment/9ced0144_cdf2b00b?usp... :
PS2, Line 20: #define PSP_VERSTAGE_STACK_START	0x42000
            : #define PSP_VERSTAGE_STACK_SIZE		(36K)
The stack size and start address is a contract between PSP Bootloader and Verstage. So changing it here alone will break that contract.

I am wondering if there are any clang compiler settings that can satisfy the memory layout requirements. Since we need to fix the original issue, let us just do `
cmos_write(RTC_FREQ_SELECT_AMD, RTC_FREQ_SELECT);` in vbnv_platform_init_cmos for now and revisit switching to cmos_init(0) later.