Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42623 )
Change subject: nb/intel/haswell: Use 16-bit ops on PCI COMMAND ......................................................................
nb/intel/haswell: Use 16-bit ops on PCI COMMAND
The PCI COMMAND register is 16 bits wide. So, do not use 32-bit PCI ops to update it.
Change-Id: I8f8d9e978f3b241cb544dd1d26e0f5fa8997d11e Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/minihd.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/42623/1
diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index c6b5a12..de2ce06 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -59,7 +59,7 @@ printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
/* Set Bus Master */ - pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Mini-HD configuration */ reg32 = read32(base + 0x100c);
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42623 )
Change subject: nb/intel/haswell: Use 16-bit ops on PCI COMMAND ......................................................................
Patch Set 3: Code-Review+2
Angel Pons has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/42623 )
Change subject: nb/intel/haswell: Use 16-bit ops on PCI COMMAND ......................................................................
Removed Verified+1 by build bot (Jenkins) no-reply@coreboot.org
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42623 )
Change subject: nb/intel/haswell: Use 16-bit ops on PCI COMMAND ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42623 )
Change subject: nb/intel/haswell: Use 16-bit ops on PCI COMMAND ......................................................................
nb/intel/haswell: Use 16-bit ops on PCI COMMAND
The PCI COMMAND register is 16 bits wide. So, do not use 32-bit PCI ops to update it.
Change-Id: I8f8d9e978f3b241cb544dd1d26e0f5fa8997d11e Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42623 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Patrick Rudolph siro@das-labor.org --- M src/northbridge/intel/haswell/minihd.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved Patrick Rudolph: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index c6b5a12..de2ce06 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -59,7 +59,7 @@ printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
/* Set Bus Master */ - pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Mini-HD configuration */ reg32 = read32(base + 0x100c);
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)