Change in coreboot[master]: soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delay

[Michael Niewöhner (Code Review)]

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48957 )

Change subject: soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delay
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soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delay

Correct the mask for the power cycle delay from 0xff to 0x1f, to
represent the actual maximum value according to Intel graphics PRM for
Haswell, Volume 2c and Intel graphics PRM for Broadwell, Volume 2c.

Change-Id: Ib187f1ca6474325475e5ae4cc1b2ffbce12f10bf
Signed-off-by: Michael Niewöhner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48957
Reviewed-by: Matt DeVillier 
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/northbridge/intel/haswell/gma.c
M src/soc/intel/broadwell/gma.c
2 files changed, 4 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Matt DeVillier: Looks good to me, approved

diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 0bca230..71d5ab6 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -273,8 +273,8 @@
    /* Setup Panel Power Cycle Delay */
    if (conf->gpu_panel_power_cycle_delay) {
    	reg32 = gtt_read(PCH_PP_DIVISOR);
-		reg32 &= ~0xff;
-		reg32 |= conf->gpu_panel_power_cycle_delay & 0xff;
+		reg32 &= ~0x1f;
+		reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f;
    	gtt_write(PCH_PP_DIVISOR, reg32);
    }

diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c
index d42eebc..c033b49 100644
--- a/src/soc/intel/broadwell/gma.c
+++ b/src/soc/intel/broadwell/gma.c
@@ -314,8 +314,8 @@
    /* Setup Panel Power Cycle Delay */
    if (conf->gpu_panel_power_cycle_delay) {
    	reg32 = gtt_read(PCH_PP_DIVISOR);
-		reg32 &= ~0xff;
-		reg32 |= conf->gpu_panel_power_cycle_delay & 0xff;
+		reg32 &= ~0x1f;
+		reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f;
    	gtt_write(PCH_PP_DIVISOR, reg32);
    }