Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS - coreboot-gerrit

5 Jul 2021


      Attention is currently required from: Sean Rhodes, SRIDHAR SIRICILLA, Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak, Angel Pons, Sridhar Siricilla, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 )
Change subject: soc/intel: Allow enable/disable ME via CMOS
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Patch Set 48:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52800/comment/87ebd14c_54206370 
PS48, Line 11: 
also adding one line here about the motivation would be helpful why we need this ?
We have hecienable UPD that manages the ME enable/disable using either PMC IPC or SMI SBI, and why this is needed?
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Gerrit-Project: coreboot
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