Change in coreboot[master]: mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed mode
Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34196 )
Change subject: mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed mode ......................................................................
mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed mode
We need to reduce the eMMC bus speed for these Apollo Lake mainboards because of a limitation on Intel side for industry use cases.
Change-Id: Ide6a1a302001c0752d149bfdab175a27c8f8cc35 Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb 5 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/34196/1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index 55e6105..d65ac4e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -44,7 +44,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1"
# Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index a627e3e..bee531f 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -45,7 +45,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1"
# Enable Vtd feature register "enable_vtd" = "1" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index a03f383..e1e79b4 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -44,7 +44,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1"
device domain 0 on device pci 00.0 on end # - Host Bridge diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 50207e0..fc9885c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -45,7 +45,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1"
device domain 0 on device pci 00.0 on end # - Host Bridge diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 5f1c985..3b28a26 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -44,7 +44,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1"
# Enable Vtd feature register "enable_vtd" = "1"
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34196 )
Change subject: mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed mode ......................................................................
Patch Set 1: Code-Review+2
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34196 )
Change subject: mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed mode ......................................................................
mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed mode
We need to reduce the eMMC bus speed for these Apollo Lake mainboards because of a limitation on Intel side for industry use cases.
Change-Id: Ide6a1a302001c0752d149bfdab175a27c8f8cc35 Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34196 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Werner Zeh werner.zeh@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb 5 files changed, 5 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index 55e6105..d65ac4e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -44,7 +44,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1"
# Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index a627e3e..bee531f 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -45,7 +45,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1"
# Enable Vtd feature register "enable_vtd" = "1" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index a03f383..e1e79b4 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -44,7 +44,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1"
device domain 0 on device pci 00.0 on end # - Host Bridge diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 50207e0..fc9885c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -45,7 +45,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1"
device domain 0 on device pci 00.0 on end # - Host Bridge diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 5f1c985..3b28a26 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -44,7 +44,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50 - register "emmc_host_max_speed" = "2" + register "emmc_host_max_speed" = "1"
# Enable Vtd feature register "enable_vtd" = "1"
-
Mario Scheithauer (Code Review) -
Martin Roth (Code Review)
-
Werner Zeh (Code Review)