Change in coreboot[master]: soc/intel/denverton_ns: Add UART Legacy mode with FSP traces

[Julien Viard de Galbert (Code Review)]

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/23623

Change subject: soc/intel/denverton_ns: Add UART Legacy mode with FSP traces
......................................................................

soc/intel/denverton_ns: Add UART Legacy mode with FSP traces

This option keeps the UART on the PCI interface so that FSP can output
its traces. It only hide it fron the PCI bus late so that Linux will
not reenumarate it but detects it as legacy (ttyS0 instead of ttyS4).

Change-Id: Id8801e178ffd8eeee78ece07da7bd6b8dbd88538
Signed-off-by: Julien Viard de Galbert 
---
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/uart.c
2 files changed, 34 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/23623/1

diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index 8d9a550..06a9c13 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -147,6 +147,11 @@
    bool "Legacy Mode"
    help
      Enable legacy UART mode
+
+config LEGACY_UART_MODE_LATE_HIDE
+	bool "Legacy Mode - Late Hide"
+	help
+	  Enable legacy UART mode but keep FSP traces
 endchoice

config ENABLE_HSUART
diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c
index ca4e8b5..13c263b 100644
--- a/src/soc/intel/denverton_ns/uart.c
+++ b/src/soc/intel/denverton_ns/uart.c
@@ -26,11 +26,23 @@
 #include <device/pci_ids.h>
 #include <soc/pci_devs.h>
 #include <console/console.h>
+#include <bootstate.h>
+#include <soc/uart.h>

static void dnv_ns_uart_read_resources(struct device *dev)
 {
    /* read resources to be visible in the log*/
    pci_dev_read_resources(dev);
+#if IS_ENABLED(CONFIG_LEGACY_UART_MODE_LATE_HIDE)
+	struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res->size = 0x8;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+	/* Do not configure membar */
+	res = find_resource(dev, PCI_BASE_ADDRESS_1);
+	res->flags = 0;
+	compact_resources(dev);
+#endif
+
 }

static struct device_operations uart_ops = {
@@ -51,3 +63,20 @@
    .vendor = PCI_VENDOR_ID_INTEL,
    .devices = uart_ids
 };
+
+#if IS_ENABLED(CONFIG_LEGACY_UART_MODE_LATE_HIDE)
+/* Hide HSUART PCI device very last when FSP no longer needs it */
+static void hide_hsuarts_cb(void *unused)
+{
+	int i;
+	uint32_t reg32;
+	printk(BIOS_DEBUG, "HIDING HSUARTs.\n");
+	for(i = DENVERTON_UARTS_TO_INI - 1; i >= 0; i--){
+		device_t uart_dev = dev_find_slot(0, PCI_DEVFN(HSUART_DEV, i));
+		reg32 = pci_read_config32(uart_dev, PCI_FUNC_RDCFG_HIDE)|1;
+		pci_write_config32(uart_dev, PCI_FUNC_RDCFG_HIDE, reg32);
+	}
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, hide_hsuarts_cb, NULL);
+#endif