Change in coreboot[master]: mb/intel/adlrvp: Set half_populated true for ADL-N

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62913 )

Change subject: mb/intel/adlrvp: Set half_populated true for ADL-N
......................................................................

mb/intel/adlrvp: Set half_populated true for ADL-N

Alder Lake-N has single memory controller with 64-bit bus width. Alder
Lake common meminit block driver considers bus width to be 128-bit and
populates the meminit data accordingly. By setting half_populated to
true, only the bottom half is populated.

Ideally, half_populated is used in platforms with multiple channels to
enable only one half of the channel. Alder Lake N has single channel,
and it would require for new structures to be defined in meminit block
driver for LPx memory configurations. In order to avoid adding new
structures, set half_populated to true. This has the same effect as
having single channel with 64-bit width.

BRANCH=NONE
TEST=Build and boot ADL-N RVP.

Signed-off-by: Usha P 
Change-Id: I2ecc3018a1ab039990ba47898ff0e0e2ede695cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62913
Reviewed-by: Rizwan Qureshi 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
1 file changed, 10 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Rizwan Qureshi: Looks good to me, approved

diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index e29b7d4..90d8302 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -47,7 +47,16 @@
    FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
    const struct mb_cfg *mem_config = variant_memory_params();
    int board_id = get_board_id();
-	const bool half_populated = false;
+
+	/*
+	 * Alder Lake common meminit block driver considers bus width to be 128-bit and
+	 * populates the meminit data accordingly. Alder Lake-N has single memory controller
+	 * with 64-bit bus width. By setting half_populated to true, only the bottom half is
+	 * populated.
+	 * TODO: Implement __weak variant_is_half_populated(void) function.
+	 */
+	const bool half_populated = (CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)
+			 || CONFIG(BOARD_INTEL_ADLRVP_N));

const struct mem_spd memory_down_spd_info = {
    	.topo = MEM_TOPO_MEMORY_DOWN,