Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50342 )
Change subject: soc/amd/cezanne: Add verstage support ......................................................................
soc/amd/cezanne: Add verstage support
Setup the config required to support verstage. The offsets are the same as picasso.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50342 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Martin Roth martinroth@google.com --- M src/soc/amd/cezanne/Kconfig 1 file changed, 21 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 530b4e7..10c085e 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -109,10 +109,31 @@ help The amount of coreboot-allocated heap and stack usage by the FSP.
+config VERSTAGE_ADDR + hex + depends on VBOOT_SEPARATE_VERSTAGE + default 0x2140000 + help + Sets the address in DRAM where verstage should be loaded if running + as a separate stage on x86. + +config VERSTAGE_SIZE + hex + depends on VBOOT_SEPARATE_VERSTAGE + default 0x80000 + help + Sets the size of DRAM allocation for verstage in linker script if + running as a separate stage on x86. + config RAMBASE hex default 0x10000000
+config RO_REGION_ONLY + string + depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A + default "apu/amdfw" + config CPU_ADDR_BITS int default 48