Change in coreboot[master]: mb, soc: Add the SPD_CACHE_ENABLE

[Zhuohao Lee (Code Review)]

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, Zhuohao Lee.
Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62294 )

Change subject: mb, soc: Add the SPD_CACHE_ENABLE
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Patch Set 3:

(1 comment)

Patchset:

PS2:
> Wait sorry I'm going crazy, you already did this? https://review.coreboot. […]

Hi Subrata/Tim,

Sorry, i could be misunderstand your meaning. I thought the original request is asking to move the below full training setting to the function read_spd_dimm() https://review.coreboot.org/c/coreboot/+/62294/3/src/soc/intel/common/block/... :

```
    if (dimms_changed) {
    	memupd->FspmArchUpd.NvsBufferPtr = 0;
    	memupd->FspmArchUpd.BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION;
    }
```

However, that change will require the FSPM_UPD *memupd be passing to the function mem_populate_channel_data() in order to pass it to the read_spd_dimm(). But the mem_populate_channel_data() is a common api and will require the other intel soc change(eg. tigerlake). https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block/...

Do we need to change it or could we just apply the current approach?