Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38846 )
Change subject: mainboard/hatch: Enable TetonGlacierMode on Puff ......................................................................
mainboard/hatch: Enable TetonGlacierMode on Puff
Allow for reconfiguring the PCIe lanes at runtime.
BUG=b:149171631 BRANCH=none TEST=none
Change-Id: Id9a72161494db6a4da4abd3302b06df7c70634ab Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38846/1
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 4ffbfed..09c109a 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -2,6 +2,9 @@ # Enable heci communication register "HeciEnabled" = "1"
+ # Auto-switch between X4 NVMe and X2 NVMe. + register "TetonGlacierMode" = "1" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, @@ -281,6 +284,7 @@ end end # FSP requires func0 be enabled. device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). + device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) device pci 1e.3 off end # GSPI #1 end
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38846 )
Change subject: mainboard/hatch: Enable TetonGlacierMode on Puff ......................................................................
Patch Set 2:
(2 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/38846/2/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38846/2/src/soc/intel/cannonlake/ch... PS2, Line 245: //
Why the C++ style comment?
why bother
https://review.coreboot.org/c/coreboot/+/38846/2/src/soc/intel/cannonlake/fs... File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/38846/2/src/soc/intel/cannonlake/fs... PS2, Line 377: //
Why the C++ style comment?
why bother
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38846 )
Change subject: soc/intel/cannonlake: Plumb TetonGlacierMode into dt ......................................................................
Patch Set 3:
(2 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/38846/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38846/2//COMMIT_MSG@6 PS2, Line 6: : mainboard/hatch
mb/google/hatch
Ack
https://review.coreboot.org/c/coreboot/+/38846/2/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38846/2/src/soc/intel/cannonlake/ch... PS2, Line 245: //
why bother
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38846 )
Change subject: soc/intel/cannonlake: Plumb TetonGlacierMode into dt ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38846/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38846/1/src/mainboard/google/hatch/... PS1, Line 6: TetonGlacierMode This doesn't exist in chip config.
https://review.coreboot.org/c/coreboot/+/38846/1/src/mainboard/google/hatch/... PS1, Line 7: I believe you also need to set PcieRpEnable for RP11.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38846 )
Change subject: soc/intel/cannonlake: Plumb TetonGlacierMode into dt ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38846/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/puff/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38846/1/src/mainboard/google/hatch/... PS1, Line 6: TetonGlacierMode
This doesn't exist in chip config.
wrong patch set version...
https://review.coreboot.org/c/coreboot/+/38846/1/src/mainboard/google/hatch/... PS1, Line 7:
I believe you also need to set PcieRpEnable for RP11.
ditto.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38846 )
Change subject: soc/intel/cannonlake: Plumb TetonGlacierMode into dt ......................................................................
Patch Set 3: Code-Review+2
Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38846 )
Change subject: soc/intel/cannonlake: Plumb TetonGlacierMode into dt ......................................................................
soc/intel/cannonlake: Plumb TetonGlacierMode into dt
The following plumbs through the enabling of Intel's TetonGlacierMode allows for reconfiguring the PCIe lanes at runtime for hybrid drives to be accessable via devicetree.
BUG=b:149171631 BRANCH=none TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration on Puff.
Change-Id: Id9a72161494db6a4da4abd3302b06df7c70634ab Signed-off-by: Edward O'Callaghan quasisec@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38846 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index fd37d26..752ec1f 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -242,6 +242,9 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled;
+ /* Enables support for Teton Glacier hybrid storage device */ + uint8_t TetonGlacierMode; + /* PL1 Override value in Watts */ uint32_t tdp_pl1_override; /* PL2 Override value in Watts */ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index f1b8446..80918f1 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -374,6 +374,9 @@ #endif params->Device4Enable = config->Device4Enable;
+ /* Teton Glacier hybrid storage support */ + params->TetonGlacierMode = config->TetonGlacierMode; + /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */
-
Angel Pons (Code Review) -
Edward O'Callaghan (Code Review)
-
Furquan Shaikh (Code Review)