[S] Change in coreboot[master]: mb/hp/z220_series: Add configs for integrated XHCI

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67089 )

(

8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/hp/z220_series: Add configs for integrated XHCI
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mb/hp/z220_series: Add configs for integrated XHCI

Without these, all SuperSpeed ports are wired to EHCI #2.

"superspeed_capable_ports" and "xhci_switchable_ports" should fit both
CMT and SFF variants, while "xhci_overcurrent_mapping" should be
consistent with the first 4 elements of mainboard_usb_ports[].

With this commit, SuperSpeed devices plugged in SuperSpeed ports are
wired to the XHCI on my own Z220 SFF.

Signed-off-by: Bill XIE 
Change-Id: Ifddecfd1d32ed6ab84d7eed8dc2d85d83cbebbcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67089
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/hp/z220_series/devicetree.cb
1 file changed, 25 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/hp/z220_series/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb
index ea8fad9..bcacf71 100644
--- a/src/mainboard/hp/z220_series/devicetree.cb
+++ b/src/mainboard/hp/z220_series/devicetree.cb
@@ -33,6 +33,9 @@
    		register "sata_interface_speed_support" = "0x3"
    		register "spi_lvscc" = "0x2005"
    		register "spi_uvscc" = "0x2005"
+			register "superspeed_capable_ports" = "0x0000000f"
+			register "xhci_switchable_ports"    = "0x0000000f"
+			register "xhci_overcurrent_mapping" = "0x0000000f"

device pci 14.0 on  end	# xHCI
    		device pci 16.0 on  end	# Management Engine Interface 1