Change in coreboot[master]: arch/riscv: Fix interrupt_handler to adapt to machine length

[Xiang W (Code Review)]

Xiang W has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53945 )

Change subject: arch/riscv: Fix interrupt_handler to adapt to machine length
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arch/riscv: Fix interrupt_handler to adapt to machine length

The length of mcause is related to the word length of the machine.
Using a constant to remove the most significant bit is not an ideal
method. This patch uses the gcc built-in macro __riscv_xlen to remove
the highest bit of mcause

Change-Id: I516fbec1dba11ce6efd3523555c48e972d2cf418
Signed-off-by: Xiang W 
---
M src/arch/riscv/trap_handler.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/53945/1

diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index 32b2c40..bebed23 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -69,7 +69,7 @@

static void interrupt_handler(trapframe *tf)
 {
-	uint64_t cause = tf->cause & ~0x8000000000000000ULL;
+	uint64_t cause = tf->cause & ~(1ULL << (__riscv_xlen - 1));

switch (cause) {
    case IRQ_M_TIMER: