Change in coreboot[master]: mb/intel/adlrvp: Configure GPIOs to enable DMIC

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47279 )

Change subject: mb/intel/adlrvp: Configure GPIOs to enable DMIC
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mb/intel/adlrvp: Configure GPIOs to enable DMIC

The patch configures GPIO pins to enable DMIC.

Signed-off-by: Sridhar Siricilla 
Change-Id: I2907737071f7d6b3c88c492d90edf8455d1fa50a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47279
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
Reviewed-by: V Sowmya 
---
M src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
1 file changed, 6 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  V Sowmya: Looks good to me, approved

diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
index c7029fc1..f91b94f 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
@@ -224,17 +224,17 @@
    /* SNDW1_DATA */
    PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
    /* SNDW2_CLK */
-	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
    /* SNDW2_DATA */
-	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
    /* SNDW3_CLK */
-	PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
    /* SNDW3_DATA */
-	PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
    /* SNDW4_CLK */
-	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
    /* SNDW4_DATA */
-	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),

/* SMB_CLK */
    PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),