Change in coreboot[master]: doc/relnotes/4.14: add Intel Xeon-SP support status change

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52735 )

Change subject: doc/relnotes/4.14: add Intel Xeon-SP support status change
......................................................................

doc/relnotes/4.14: add Intel Xeon-SP support status change

Signed-off-by: Jonathan Zhang 
Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52735
Reviewed-by: Angel Pons 
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
---
M Documentation/releases/coreboot-4.14-relnotes.md
1 file changed, 24 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md
index b6c927e..3593bdc 100644
--- a/Documentation/releases/coreboot-4.14-relnotes.md
+++ b/Documentation/releases/coreboot-4.14-relnotes.md
@@ -76,4 +76,28 @@
 for common ACPI GNVS table entries were largely moved to one centralized
 implementation.

+### Intel Xeon Scalable Processor support is now considered mature
+
+Intel Xeon Scalable Processor (Xeon-SP) family [1] is designed
+primarily to serve the needs of the server market.
+
+coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory.
+This release has support for SkyLake-SP (SKX-SP) which is the 2nd
+generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation
+or the latest generation [2] on market.
+
+With this release, the codebase for multiple generations of Xeon-SP
+were unified and optimized:
+* SKX-SP SoC code is used in OCP TiogaPass mainboard [3]. Support for
+this board is in Proof Of Concept Status.
+* CPX-SP SoC code is used in OCP DeltaLake mainboard. Support for
+this board is in DVT (Design Validation Test) exit equivalent status.
+Features supported, (performance/stability) test scopes, known issues,
+features gaps are described in [4].
+
 ### Add significant changes here
+
+[1] https://www.intel.com/content/www/us/en/products/details/processors/xeon/sca...
+[2] https://www.intel.com/content/www/us/en/products/docs/processors/xeon/3rd-ge...
+[3] ../mainboard/ocp/tiogapass.md
+[4] ../mainboard/ocp/deltalake.md