Change in coreboot[master]: [WIP] mb/adlrvp: Add UART0 gpio config for ADL-M RVP

[Anil Kumar K (Code Review)]

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52201 )

Change subject: [WIP] mb/adlrvp: Add UART0 gpio config for ADL-M RVP
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[WIP] mb/adlrvp: Add UART0 gpio config for ADL-M RVP

- UART0 config was missing in early gpio table

Signed-off-by: Anil Kumar 
Change-Id: Ic0cc955a02936b74f44fed55a9f4b8054646681a
---
M src/mainboard/intel/adlrvp/early_gpio_m.c
1 file changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/52201/1

diff --git a/src/mainboard/intel/adlrvp/early_gpio_m.c b/src/mainboard/intel/adlrvp/early_gpio_m.c
index c257004..da02c83 100644
--- a/src/mainboard/intel/adlrvp/early_gpio_m.c
+++ b/src/mainboard/intel/adlrvp/early_gpio_m.c
@@ -13,7 +13,17 @@
    PAD_CFG_GPO(GPP_A8, 1, DEEP),
 };

+static const struct pad_config early_uart_gpio_table[] = {
+        /* UART0 RX */
+        PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+        /* UART0 TX */
+        PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+};
+
 void variant_configure_early_gpio_pads(void)
 {
+	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
+		gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table));
+
    gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
 }