Change in coreboot[master]: soc/intel/common/cse: Add function to perform CSE lock configuration
Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Werner Zeh, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 )
Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration ......................................................................
Patch Set 6:
(2 comments)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/61520/comment/33bd52f8_e5f13bed PS5, Line 1014: /*
Ack ?
means?
When you acknowledge it's you had wrong understanding this code don't need any change (as you have initially suggested in line 1014) then folks ideally *click* on the ACK to close the thread.
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/61520/comment/2c0a0757_ae041265 PS6, Line 1018: (cse_is_hfs1_com_normal() || cse_is_hfs1_com_soft_temp_disable())
3rd para says. "Furthermore, if Intel® CSME is in ERROR state, **BIOS** can use I/O 0xCF9 write of >06h or 0Eh command with PMC PWRM offset 1048h register bit [20] CF9GR set to perform the global reset
I commented based on 3rd para you posted in this comment thread. Can you please create crosbug, we can discuss further there?
I'm also specific about 3rd para that says about error condition in CSE.
**When CSE is always in bad state then how can one follow #2 so the only way is #1 hence, we should avoid locking the PMC cf9.**
Based on my reply above, please let me know if you still have some more opens? Do we still need a dedicated crossbus for such chipset configuration discussion ?
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Subrata Banik (Code Review)