Change in coreboot[master]: soc/intel/elkhartlake: Update FADT table

[Lean Sheng Tan (Code Review)]

Attention is currently required from: Patrick Rudolph.
Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55049 )

Change subject: soc/intel/elkhartlake: Update FADT table
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soc/intel/elkhartlake: Update FADT table

Update FADT table per relevant PM settings:
Fix PM Timer block access size and disable C2 and C3 states for the CPU.
Further on, set the century byte offset in FADT to point to the common location in CMOS.

Signed-off-by: Lean Sheng Tan  Change-Id: I72a57bf8ec61c3eabc4522c2695ae4b16979f188
Change-Id: Ie2f3468cd3da2ab66802e5d7765b5e5b4dc26bbe
---
M src/soc/intel/elkhartlake/acpi.c
1 file changed, 6 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/55049/1

diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c
index 0006b5f..a0c966e 100644
--- a/src/soc/intel/elkhartlake/acpi.c
+++ b/src/soc/intel/elkhartlake/acpi.c
@@ -156,9 +156,14 @@
    fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
    fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
    fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED;
+	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
    fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
    fadt->x_pm_tmr_blk.addrh = 0x0;
+	fadt->preferred_pm_profile = PM_MOBILE;
+	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+	fadt->duty_width = 0x3;	/* CLK_VAL bits 3:1 */
+	fadt->century = 0x32;

if (config->s0ix_enable)
    	fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;