Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38505 )
Change subject: mb/intel/tglrvp: Enable SATA ......................................................................
mb/intel/tglrvp: Enable SATA
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/38505/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index fbd1c39..851b30e 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -45,6 +45,11 @@ register "PcieClkSrcUsage[2]" = "0x3" register "PcieClkSrcUsage[3]" = "0x8"
+ register "SataEnable" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci,
Wonkyu Kim has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/38505 )
Change subject: mb/intel/tglrvp: Enable SATA ......................................................................
mb/intel/tglrvp: Enable SATA
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/38505/2
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38505 )
Change subject: mb/intel/tglrvp: Enable SATA ......................................................................
Patch Set 2: Code-Review+1
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38505 )
Change subject: mb/intel/tglrvp: Enable SATA ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38505/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38505/3/src/mainboard/intel/tglrvp/... PS3, Line 47: : register "SataEnable" = "1" do you still need this config as i could see below code, you have relied on .cb on/off options
https://review.coreboot.org/c/coreboot/+/38504/3/src/soc/intel/tigerlake/fsp...
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38505
to look at the new patch set (#4).
Change subject: mb/intel/tglrvp: Enable SATA ......................................................................
mb/intel/tglrvp: Enable SATA
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/38505/4
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38505 )
Change subject: mb/intel/tglrvp: Enable SATA ......................................................................
Patch Set 4: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/38505/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38505/3/src/mainboard/intel/tglrvp/... PS3, Line 47: : register "SataEnable" = "1"
do you still need this config as i could see below code, you have relied on .cb on/off options […]
Ack
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38505 )
Change subject: mb/intel/tglrvp: Enable SATA ......................................................................
Patch Set 4: Code-Review+2
Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38505 )
Change subject: mb/intel/tglrvp: Enable SATA ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38505/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38505/4//COMMIT_MSG@8 PS4, Line 8: : BUG=none : BRANCH=none : TEST=Build and boot tigerlake rvp board with SATA memory please add some lines about what changes are made in code.
Wonkyu Kim has uploaded a new patch set (#5) to the change originally created by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/38505 )
Change subject: mb/intel/tglrvp: Enable SATA ......................................................................
mb/intel/tglrvp: Enable SATA
Enable both SATA ports for TGLRVP.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/38505/5
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38505 )
Change subject: mb/intel/tglrvp: Enable SATA ......................................................................
Patch Set 5: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/38505/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38505/4//COMMIT_MSG@8 PS4, Line 8: : BUG=none : BRANCH=none : TEST=Build and boot tigerlake rvp board with SATA memory
please add some lines about what changes are made in code.
Ack
Wonkyu Kim has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/38505 )
Change subject: mb/intel/tglrvp: Enable SATA ......................................................................
Removed Code-Review+1 by Wonkyu Kim wonkyu.kim@intel.corp-partner.google.com
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38505 )
Change subject: mb/intel/tglrvp: Enable SATA ......................................................................
Patch Set 5: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38505 )
Change subject: mb/intel/tglrvp: Enable SATA ......................................................................
mb/intel/tglrvp: Enable SATA
Enable both SATA ports for TGLRVP.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38505 Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Subrata Banik subrata.banik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Nick Vaccaro: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index fbd1c39..01e0f3f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -45,6 +45,10 @@ register "PcieClkSrcUsage[2]" = "0x3" register "PcieClkSrcUsage[3]" = "0x8"
+ register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -122,7 +126,7 @@ device pci 16.3 off end # CSME 0xA0E3 device pci 16.4 off end # HECI3 0xA0E4 device pci 16.5 off end # HECI4 0xA0E5 - device pci 17.0 off end # SATA 0xA0D3 + device pci 17.0 on end # SATA 0xA0D3 device pci 19.0 off end # I2C4 0xA0C5 device pci 19.1 on end # I2C5 0xA0C6 device pci 19.2 on end # UART2 0xA0C7
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38505 )
Change subject: mb/intel/tglrvp: Enable SATA ......................................................................
Patch Set 6:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/240 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/239 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/238
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Nick Vaccaro (Code Review)
-
Pratikkumar V Prajapati (Code Review)
-
Subrata Banik (Code Review)
-
Wonkyu Kim (Code Review)