Change in coreboot[master]: soc/intel/common: Add common Intel timer code

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/19911 )

Change subject: soc/intel/common: Add common Intel timer code
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soc/intel/common: Add common Intel timer code

Add common timer code to get tsc frequency(Mhz).

Change-Id: Ifd4b24735c74c636348fc32afbcc267e384cb610
Signed-off-by: Aamir Bohra 
---
A src/soc/intel/common/block/timer/Kconfig
A src/soc/intel/common/block/timer/Makefile.inc
A src/soc/intel/common/block/timer/timer.c
3 files changed, 37 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/19911/2

diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig
new file mode 100644
index 0000000..a415045
--- /dev/null
+++ b/src/soc/intel/common/block/timer/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_TIMER
+	bool
+	help
+	  Intel Processor common TIMER support
diff --git a/src/soc/intel/common/block/timer/Makefile.inc b/src/soc/intel/common/block/timer/Makefile.inc
new file mode 100644
index 0000000..b562c50
--- /dev/null
+++ b/src/soc/intel/common/block/timer/Makefile.inc
@@ -0,0 +1,6 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c
+postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c
diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c
new file mode 100644
index 0000000..c93aebd
--- /dev/null
+++ b/src/soc/intel/common/block/timer/timer.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <intelblocks/msr.h>
+
+/* CPU bus clock is fixed at 100MHz */
+#define CPU_BCLK		100
+
+unsigned long tsc_freq_mhz(void)
+{
+	msr_t msr = rdmsr(MSR_PLATFORM_INFO);
+	return (CPU_BCLK * ((msr.lo >> 8) & 0xff));
+}