Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40919 )
Change subject: soc/intel/xeon_sp: Add C620 p2sb.h ......................................................................
soc/intel/xeon_sp: Add C620 p2sb.h
Add p2sb.h that is shared by all currently supported Xeon SP CPUs.
Change-Id: Idcbff7ad587cb116897a953c079fb0a8b86cc2ed Signed-off-by: Andrey Petrov anpetrov@fb.com --- A src/soc/intel/xeon_sp/include/soc/p2sb.h 1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/40919/1
diff --git a/src/soc/intel/xeon_sp/include/soc/p2sb.h b/src/soc/intel/xeon_sp/include/soc/p2sb.h new file mode 100644 index 0000000..3a96072 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/p2sb.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* + * Currently all known xeon-sp CPUs use C620 PCH. These definitions + * come from C620 datasheet. + */ + +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) +#define PCH_P2SB_EPMASK0 0xb0 +#define P2SB_SIZE 0x1000000
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40919 )
Change subject: soc/intel/xeon_sp: Add C620 p2sb.h ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/40919/2/src/soc/intel/xeon_sp/inclu... File src/soc/intel/xeon_sp/include/soc/p2sb.h:
https://review.coreboot.org/c/coreboot/+/40919/2/src/soc/intel/xeon_sp/inclu... PS2, Line 6: C620 datasheet ... C620 datasheet (Intel Doc #336067-007US).
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40919 )
Change subject: soc/intel/xeon_sp: Add C620 p2sb.h ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40919/2/src/soc/intel/xeon_sp/inclu... File src/soc/intel/xeon_sp/include/soc/p2sb.h:
https://review.coreboot.org/c/coreboot/+/40919/2/src/soc/intel/xeon_sp/inclu... PS2, Line 6: C620 datasheet
... C620 datasheet (Intel Doc #336067-007US).
Done
Hello build bot (Jenkins), Maxim Polyakov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40919
to look at the new patch set (#3).
Change subject: soc/intel/xeon_sp: Add C620 p2sb.h ......................................................................
soc/intel/xeon_sp: Add C620 p2sb.h
Add p2sb.h that is shared by all currently supported Xeon SP CPUs.
Change-Id: Idcbff7ad587cb116897a953c079fb0a8b86cc2ed Signed-off-by: Andrey Petrov anpetrov@fb.com --- A src/soc/intel/xeon_sp/include/soc/p2sb.h 1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/40919/3
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40919 )
Change subject: soc/intel/xeon_sp: Add C620 p2sb.h ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40919/3/src/soc/intel/xeon_sp/inclu... File src/soc/intel/xeon_sp/include/soc/p2sb.h:
https://review.coreboot.org/c/coreboot/+/40919/3/src/soc/intel/xeon_sp/inclu... PS3, Line 8: #include <commonlib/helpers.h>
https://review.coreboot.org/c/coreboot/+/40919/3/src/soc/intel/xeon_sp/inclu... PS3, Line 12: 0x1000000 (16 * MiB)
Hello build bot (Jenkins), Maxim Polyakov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40919
to look at the new patch set (#4).
Change subject: soc/intel/xeon_sp: Add C620 p2sb.h ......................................................................
soc/intel/xeon_sp: Add C620 p2sb.h
Add p2sb.h that is shared by all currently supported Xeon SP CPUs.
Change-Id: Idcbff7ad587cb116897a953c079fb0a8b86cc2ed Signed-off-by: Andrey Petrov anpetrov@fb.com --- A src/soc/intel/xeon_sp/include/soc/p2sb.h 1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/40919/4
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40919 )
Change subject: soc/intel/xeon_sp: Add C620 p2sb.h ......................................................................
Patch Set 4: Code-Review+2
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40919 )
Change subject: soc/intel/xeon_sp: Add C620 p2sb.h ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40919/3/src/soc/intel/xeon_sp/inclu... File src/soc/intel/xeon_sp/include/soc/p2sb.h:
https://review.coreboot.org/c/coreboot/+/40919/3/src/soc/intel/xeon_sp/inclu... PS3, Line 8:
#include <commonlib/helpers. […]
Done
https://review.coreboot.org/c/coreboot/+/40919/3/src/soc/intel/xeon_sp/inclu... PS3, Line 12: 0x1000000
(16 * MiB)
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40919 )
Change subject: soc/intel/xeon_sp: Add C620 p2sb.h ......................................................................
Patch Set 4: Code-Review+2
Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40919 )
Change subject: soc/intel/xeon_sp: Add C620 p2sb.h ......................................................................
soc/intel/xeon_sp: Add C620 p2sb.h
Add p2sb.h that is shared by all currently supported Xeon SP CPUs.
Change-Id: Idcbff7ad587cb116897a953c079fb0a8b86cc2ed Signed-off-by: Andrey Petrov anpetrov@fb.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/40919 Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/soc/intel/xeon_sp/include/soc/p2sb.h 1 file changed, 14 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Maxim Polyakov: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/include/soc/p2sb.h b/src/soc/intel/xeon_sp/include/soc/p2sb.h new file mode 100644 index 0000000..b90bc73 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/p2sb.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <commonlib/helpers.h> + +/* + * Currently all known xeon-sp CPUs use C620 PCH. These definitions + * come from C620 datasheet (Intel Doc #336067-007US) + */ + +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) +#define PCH_P2SB_EPMASK0 0xb0 +#define P2SB_SIZE (16 * MiB)
-
Andrey Petrov (Code Review) -
Angel Pons (Code Review)
-
Maxim Polyakov (Code Review)