Change in coreboot[master]: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per SKL EDS

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38514 )

Change subject: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per SKL EDS
......................................................................

soc/intel/skylake: Update 64 bit SA DRAM bit fields as per SKL EDS

TEST=Build and boot EVE and Soraka to OS.

Change-Id: Ia32723444c044572fbcecce151d89e739e570b3b
Signed-off-by: Subrata Banik 
---
M src/soc/intel/skylake/acpi/systemagent.asl
1 file changed, 7 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/38514/1

diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
index f826ba5..291c37b 100644
--- a/src/soc/intel/skylake/acpi/systemagent.asl
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -32,26 +32,27 @@
    	Offset(0x40),	/* EPBAR (0:0:0:40) */
    	EPEN, 1,	/* Enable */
    	, 11,
-		EPBR, 20,	/* EPBAR [31:12] */
+		EPBR, 27,	/* EPBAR [38:12] */

Offset(0x48),	/* MCHBAR (0:0:0:48) */
    	MHEN, 1,	/* Enable */
    	, 14,
-		MHBR, 17,	/* MCHBAR [31:15] */
+		MHBR, 24,	/* MCHBAR [38:15] */

Offset(0x60),	/* PCIEXBAR (0:0:0:60) */
    	PXEN, 1,	/* Enable */
    	PXSZ, 2,	/* PCI Express Size */
-		, 23,
-		PXBR, 6,	/* PCI Express BAR [31:26] */
+		, 25,
+		PXBR, 11,	/* PCI Express BAR [38:28] */

Offset(0x68),	/* DMIBAR (0:0:0:68) */
    	DIEN, 1,	/* Enable */
    	, 11,
-		DIBR, 20,	/* DMIBAR [31:12] */
+		DIBR, 27,	/* DMIBAR [38:12] */

Offset (0x70),	/* ME Base Address */
    	MEBA, 64,
+
    	Offset (0xa0),
    	TOM, 64,	/* Top of Used Memory */
    	TUUD, 64,	/* Top of Upper Used Memory */
@@ -246,7 +247,7 @@
 /* Get PCIe BAR */
 Method (GPCB, 0, Serialized)
 {
-	ShiftLeft (_SB.PCI0.MCHC.PXBR, 26, Local0)
+	ShiftLeft (_SB.PCI0.MCHC.PXBR, 28, Local0)
    Return (Local0)
 }

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38514 )

Change subject: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per SKL EDS
......................................................................

Patch Set 2: Code-Review+1

(2 comments)

https://review.coreboot.org/c/coreboot/+/38514/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38514/2//COMMIT_MSG@7 
PS2, Line 7: EDS
Note: The datasheet vol 2 (doc 332688) has the same values. It's not a surprise, though: the datasheets are derived from the EDS.

https://review.coreboot.org/c/coreboot/+/38514/2/src/soc/intel/skylake/acpi/... 
File src/soc/intel/skylake/acpi/systemagent.asl:

https://review.coreboot.org/c/coreboot/+/38514/2/src/soc/intel/skylake/acpi/... 
PS2, Line 46: 28
The datasheet (doc 332688) says that bits 27 and 26 are either part of the PCIEXBAR field or part of the addres mask depending on the value of LENGTH (ACPI PXSZ) field. Does it matter much?

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38514 )

Change subject: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per SKL EDS
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38514/2/src/soc/intel/skylake/acpi/... 
File src/soc/intel/skylake/acpi/systemagent.asl:

https://review.coreboot.org/c/coreboot/+/38514/2/src/soc/intel/skylake/acpi/... 
PS2, Line 46: 28
> The datasheet (doc 332688) says that bits 27 and 26 are either part of the PCIEXBAR field or part of […]

i will modify this patchset and https://review.coreboot.org/c/coreboot/+/38456 as well, it should start from 26bit as value of LENGTH also matter in total base calculation

Change in coreboot[master]: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet

[Subrata Banik (Code Review)]

Hello Patrick Rudolph, Angel Pons, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38514

to look at the new patch set (#3).

Change subject: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet
......................................................................

soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet

This patch updates SA DRAM registers bit definitions as per
SKL datasheet vol 2, doc 332688.

TEST=Build and boot EVE and Soraka to OS.

Change-Id: Ia32723444c044572fbcecce151d89e739e570b3b
Signed-off-by: Subrata Banik 
---
M src/soc/intel/skylake/acpi/systemagent.asl
1 file changed, 5 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/38514/3

Change in coreboot[master]: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38514 )

Change subject: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38514/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38514/2//COMMIT_MSG@7 
PS2, Line 7: EDS
> Note: The datasheet vol 2 (doc 332688) has the same values. […]

Ack

https://review.coreboot.org/c/coreboot/+/38514/2/src/soc/intel/skylake/acpi/... 
File src/soc/intel/skylake/acpi/systemagent.asl:

https://review.coreboot.org/c/coreboot/+/38514/2/src/soc/intel/skylake/acpi/... 
PS2, Line 46: 28
> i will modify this patchset and https://review.coreboot. […]

Ack

Change in coreboot[master]: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38514 )

Change subject: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38514 )

Change subject: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet
......................................................................

soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet

This patch updates SA DRAM registers bit definitions as per
SKL datasheet vol 2, doc 332688.

TEST=Build and boot EVE and Soraka to OS.

Change-Id: Ia32723444c044572fbcecce151d89e739e570b3b
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38514
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/soc/intel/skylake/acpi/systemagent.asl
1 file changed, 5 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
index 920062c..e430b43 100644
--- a/src/soc/intel/skylake/acpi/systemagent.asl
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -32,26 +32,27 @@
    	Offset(0x40),	/* EPBAR (0:0:0:40) */
    	EPEN, 1,	/* Enable */
    	, 11,
-		EPBR, 20,	/* EPBAR [31:12] */
+		EPBR, 27,	/* EPBAR [38:12] */

Offset(0x48),	/* MCHBAR (0:0:0:48) */
    	MHEN, 1,	/* Enable */
    	, 14,
-		MHBR, 17,	/* MCHBAR [31:15] */
+		MHBR, 24,	/* MCHBAR [38:15] */

Offset(0x60),	/* PCIEXBAR (0:0:0:60) */
    	PXEN, 1,	/* Enable */
    	PXSZ, 2,	/* PCI Express Size */
    	, 23,
-		PXBR, 6,	/* PCI Express BAR [31:26] */
+		PXBR, 13,	/* PCI Express BAR [38:26] */

Offset(0x68),	/* DMIBAR (0:0:0:68) */
    	DIEN, 1,	/* Enable */
    	, 11,
-		DIBR, 20,	/* DMIBAR [31:12] */
+		DIBR, 27,	/* DMIBAR [38:12] */

Offset (0x70),	/* ME Base Address */
    	MEBA, 64,
+
    	Offset (0xa0),
    	TOM, 64,	/* Top of Used Memory */
    	TUUD, 64,	/* Top of Upper Used Memory */

Change in coreboot[master]: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38514 )

Change subject: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet
......................................................................

Patch Set 4:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/280
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/279
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/278

Please note: This test is under development and might not be accurate at all!