Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77001?usp=email )
Change subject: SNB+MRC mainboards: Post-Haswell cleanup ......................................................................
SNB+MRC mainboards: Post-Haswell cleanup
For sandybridge boards with MRC raminit support and no soldered memory, stop replacing the entire PEI data structure, instead fill only data that cannot be had elsewhere.
Drop mainboard_get_spd() for native raminit as Haswell-style mb_get_spd_map() takes its place.
Drop unused includes as well.
Change-Id: Ie42bd1702e6e732e4cd0b7c07841d76c5079547b Signed-off-by: Keith Hui buurin@gmail.com --- M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/early_init.c M src/mainboard/intel/emeraldlake2/early_init.c M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/samsung/stumpy/early_init.c 6 files changed, 100 insertions(+), 253 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/77001/1
diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 6e51f2f..3c42516 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -1,12 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/hpet.h> -#include <stdint.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h>
void mainboard_late_rcba_config(void) { @@ -66,12 +61,6 @@ { 0, 0, -1 }, /* P13: Empty */ };
-void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} - void mb_get_spd_map(struct spd_info *spdi) { spdi->addresses[0] = 0x50; @@ -80,45 +69,26 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, - .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, - .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, - .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_BASE_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .ddr3lv_support = 0, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* enabled USB oc pin length */ - { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ - { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ - { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ - { 0, 0, 0x0000 }, /* P3: Empty */ - { 0, 0, 0x0000 }, /* P4: Empty */ - { 0, 0, 0x0000 }, /* P5: Empty */ - { 0, 0, 0x0000 }, /* P6: Empty */ - { 0, 0, 0x0000 }, /* P7: Empty */ - { 0, 4, 0x0000 }, /* P8: Empty */ - { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ - { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ - { 0, 4, 0x0000 }, /* P11: Empty */ - { 0, 4, 0x0000 }, /* P12: Empty */ - { 0, 4, 0x0000 }, /* P13: Empty */ - }, - .ddr_refresh_rate_config = 2, /* Force double refresh rate */ + uint16_t usbcfg[16][3] = { + /* enabled USB oc pin length */ + { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ + { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ + { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ + { 0, 0, 0x0000 }, /* P3: Empty */ + { 0, 0, 0x0000 }, /* P4: Empty */ + { 0, 0, 0x0000 }, /* P5: Empty */ + { 0, 0, 0x0000 }, /* P6: Empty */ + { 0, 0, 0x0000 }, /* P7: Empty */ + { 0, 4, 0x0000 }, /* P8: Empty */ + { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ + { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ + { 0, 4, 0x0000 }, /* P11: Empty */ + { 0, 4, 0x0000 }, /* P12: Empty */ + { 0, 4, 0x0000 }, /* P13: Empty */ }; - *pei_data = pei_data_template; + + memcpy(pei_data->usb_port_config, &usbcfg, sizeof(usbcfg)); + + pei_data->system_type = 0; // 0 Mobile, 1 Desktop/Server + pei_data->max_ddr3_freq = 1600; } diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index 1a605fc..5cf366f 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -1,10 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/hpet.h> -#include <stdint.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include "ec/compal/ene932/ec.h" @@ -52,46 +48,29 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, - .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, - .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, - .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_BASE_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ - { 0, 3, 0x0000 }, /* P0: Empty */ - { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ - { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ - { 1, 1, 0x0040 }, /* P3: Left USB 3 (OC1) */ - { 0, 3, 0x0000 }, /* P4: Empty */ - { 0, 3, 0x0000 }, /* P5: Empty */ - { 0, 3, 0x0000 }, /* P6: Empty */ - { 0, 3, 0x0000 }, /* P7: Empty */ - /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ - { 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */ - { 0, 4, 0x0000 }, /* P9: Empty */ - { 1, 4, 0x0040 }, /* P10: Camera (no OC) */ - { 0, 4, 0x0000 }, /* P11: Empty */ - { 0, 4, 0x0000 }, /* P12: Empty */ - { 0, 4, 0x0000 }, /* P13: Empty */ - }, + uint16_t usbcfg[16][3] = { + /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ + { 0, 3, 0x0000 }, /* P0: Empty */ + { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ + { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ + { 1, 1, 0x0040 }, /* P3: Left USB 3 (OC1) */ + { 0, 3, 0x0000 }, /* P4: Empty */ + { 0, 3, 0x0000 }, /* P5: Empty */ + { 0, 3, 0x0000 }, /* P6: Empty */ + { 0, 3, 0x0000 }, /* P7: Empty */ + /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ + { 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */ + { 0, 4, 0x0000 }, /* P9: Empty */ + { 1, 4, 0x0040 }, /* P10: Camera (no OC) */ + { 0, 4, 0x0000 }, /* P11: Empty */ + { 0, 4, 0x0000 }, /* P12: Empty */ + { 0, 4, 0x0000 }, /* P13: Empty */ }; - *pei_data = pei_data_template; + + memcpy(pei_data->usb_port_config, &usbcfg, sizeof(usbcfg)); + + pei_data->system_type = 0; // 0 Mobile, 1 Desktop/Server + pei_data->max_ddr3_freq = 1600; }
const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -113,12 +92,6 @@ { 0, 0, -1 }, /* P13: Empty */ };
-void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} - void mb_get_spd_map(struct spd_info *spdi) { spdi->addresses[0] = 0x50; diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 5e0bd61..c756e11 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -1,11 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/hpet.h> -#include <stdint.h> #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <bootmode.h> @@ -81,12 +78,6 @@ } }
-void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} - void mb_get_spd_map(struct spd_info *spdi) { spdi->addresses[0] = 0x50; @@ -95,27 +86,7 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, - .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, - .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, - .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_BASE_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .max_ddr3_freq = 1600, - .usb_port_config = { + uint16_t usbcfg[16][3] = { /* enabled USB oc pin length */ { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */ { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */ @@ -131,15 +102,17 @@ { 0, 5, 0x0000 }, /* P11: Empty */ { 0, 5, 0x0000 }, /* P12: Empty */ { 1, 5, 0x0040 }, /* P13: Bluetooth (no OC) */ - }, - .usb3 = { - .mode = XHCI_MODE, - .hs_port_switch_mask = XHCI_PORTS, - .preboot_support = XHCI_PREBOOT, - .xhci_streams = XHCI_STREAMS, - }, }; - *pei_data = pei_data_template; + + memcpy(pei_data->usb_port_config, &usbcfg, sizeof(usbcfg)); + + pei_data->system_type = 0; // 0 Mobile, 1 Desktop/Server + pei_data->max_ddr3_freq = 1600; + + pei_data->usb3.mode = XHCI_MODE; + pei_data->usb3.hs_port_switch_mask = XHCI_PORTS; + pei_data->usb3.preboot_support = XHCI_PREBOOT; + pei_data->usb3.xhci_streams = XHCI_STREAMS; }
void mainboard_early_init(int s3resume) diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 2e31b23..0232fa6 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -1,15 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/hpet.h> #include <bootblock_common.h> #include <stdint.h> #include <arch/io.h> #include <superio/smsc/sio1007/sio1007.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h>
#define SIO_PORT 0x164e
@@ -50,44 +46,26 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, - .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, - .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, - .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_BASE_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 0, - .max_ddr3_freq = 1600, - .usb_port_config = { - { 1, 0, 0x0040 }, /* P0: Front port (OC0) */ - { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ - { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ - { 1, 2, 0x0040 }, /* P4: Front port (OC2) */ - { 0, 0, 0x0000 }, /* P5: Empty */ - { 0, 0, 0x0000 }, /* P6: Empty */ - { 0, 0, 0x0000 }, /* P7: Empty */ - { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ - { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ - { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ - { 0, 4, 0x0000 }, /* P11: Empty */ - { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ - { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ - }, + uint16_t usbcfg[16][3] = { + { 1, 0, 0x0040 }, /* P0: Front port (OC0) */ + { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ + { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ + { 1, 2, 0x0040 }, /* P4: Front port (OC2) */ + { 0, 0, 0x0000 }, /* P5: Empty */ + { 0, 0, 0x0000 }, /* P6: Empty */ + { 0, 0, 0x0000 }, /* P7: Empty */ + { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ + { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ + { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ + { 0, 4, 0x0000 }, /* P11: Empty */ + { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ + { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ }; - *pei_data = pei_data_template; + + memcpy(pei_data->usb_port_config, &usbcfg, sizeof(usbcfg)); + + pei_data->max_ddr3_freq = 1600; }
const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -108,12 +86,6 @@ { 1, 0, 5 }, /* P13: Back port (OC5) */ };
-void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} - void mb_get_spd_map(struct spd_info *spdi) { spdi->addresses[0] = 0x50; diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index c422842..bdf3619 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -1,13 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/hpet.h> #include <bootblock_common.h> -#include <stdint.h> #include <device/pnp_def.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -55,54 +52,34 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, - .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, - .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, - .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_BASE_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, /* 0 Mobile, 1 Desktop/Server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .gbe_enable = 1, - .ddr3lv_support = 0, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* enabled USB oc pin length */ - { 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */ - { 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */ - { 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */ - { 1, 0, 0x0040 }, /* P3: upper right USB 3.0 (OC0) */ - { 1, 0, 0x0040 }, /* P4: lower USB 2.0 (OC0) */ - { 1, 0, 0x0040 }, /* P5: upper USB 2.0 (OC0) */ - { 1, 0, 0x0040 }, /* P6: front panel USB 2.0 (OC0) */ - { 1, 0, 0x0040 }, /* P7: front panel USB 2.0 (OC0) */ - { 1, 4, 0x0040 }, /* P8: internal USB 2.0 (OC4) */ - { 1, 4, 0x0040 }, /* P9: internal USB 2.0 (OC4) */ - { 1, 4, 0x0040 }, /* P10: internal USB 2.0 (OC4) */ - { 1, 4, 0x0040 }, /* P11: internal USB 2.0 (OC4) */ - { 1, 4, 0x0040 }, /* P12: internal USB 2.0 (OC4) */ - { 1, 4, 0x0040 }, /* P13: internal USB 2.0 (OC4) */ - }, - .usb3 = { - .mode = 3, /* Smart Auto? */ - .hs_port_switch_mask = 0xf, /* All four ports. */ - .preboot_support = 1, /* preOS driver? */ - .xhci_streams = 1, /* Enable. */ - }, - .pcie_init = 1, + uint16_t usbcfg[16][3] = { + /* enabled USB oc pin length */ + { 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */ + { 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */ + { 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */ + { 1, 0, 0x0040 }, /* P3: upper right USB 3.0 (OC0) */ + { 1, 0, 0x0040 }, /* P4: lower USB 2.0 (OC0) */ + { 1, 0, 0x0040 }, /* P5: upper USB 2.0 (OC0) */ + { 1, 0, 0x0040 }, /* P6: front panel USB 2.0 (OC0) */ + { 1, 0, 0x0040 }, /* P7: front panel USB 2.0 (OC0) */ + { 1, 4, 0x0040 }, /* P8: internal USB 2.0 (OC4) */ + { 1, 4, 0x0040 }, /* P9: internal USB 2.0 (OC4) */ + { 1, 4, 0x0040 }, /* P10: internal USB 2.0 (OC4) */ + { 1, 4, 0x0040 }, /* P11: internal USB 2.0 (OC4) */ + { 1, 4, 0x0040 }, /* P12: internal USB 2.0 (OC4) */ + { 1, 4, 0x0040 }, /* P13: internal USB 2.0 (OC4) */ }; - *pei_data = pei_data_template; + + memcpy(pei_data->usb_port_config, &usbcfg, sizeof(usbcfg)); + + pei_data->max_ddr3_freq = 1600; + pei_data->pcie_init = 1; + pei_data->ec_present = 1; + pei_data->gbe_enable = 1; + pei_data->usb3.hs_port_switch_mask = 0xf; + pei_data->usb3.mode = 3; + pei_data->usb3.preboot_support = 1; + pei_data->usb3.xhci_streams = 1; }
const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -123,12 +100,6 @@ { 1, 0, 4 }, /* P13: internal USB 2.0 (OC4) */ };
-void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} - void mb_get_spd_map(struct spd_info *spdi) { spdi->addresses[0] = 0x50; diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index bc523e6..deac337 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -1,16 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <arch/hpet.h> #include <bootblock_common.h> -#include <stdint.h> #include <pc80/mc146818rtc.h> -#include <console/console.h> #include <bootmode.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> -#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <superio/smsc/lpc47n207/lpc47n207.h> @@ -91,7 +87,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - uint8_t spdaddr[] = {0xa0, 0x00, 0xa4, 0x00}; uint16_t usbcfg[16][3] = { { 1, 0, 0x0080 }, /* P0: Front port (OC0) */ { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ @@ -110,7 +105,6 @@ };
memcpy(pei_data->usb_port_config, &usbcfg, sizeof(usbcfg)); - memcpy(pei_data->spd_addresses, &spdaddr, sizeof(spdaddr));
pei_data->system_type = 0; // 0 Mobile, 1 Desktop/Server } @@ -121,12 +115,6 @@ spdi->addresses[2] = 0x52; }
-void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { /* enabled power USB oc pin */ { 1, 1, 0 }, /* P0: Front port (OC0) */
-
Keith Hui (Code Review)