Change in coreboot[master]: soc/intel/braswell: CACHE_MRC_SETTINGS depends on !VBOOT_START_IN_ROM... - coreboot-gerrit

7 Apr 2021


      Attention is currently required from: Frans Hendriks, Patrick Rudolph, Wim Vervoorn.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52128 )
Change subject: soc/intel/braswell: CACHE_MRC_SETTINGS depends on !VBOOT_START_IN_ROMSTAGE
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Patch Set 7:
(1 comment)
Patchset:
PS7:
...
I noticed your concern in raminit_common(). 
Should disable_save_data be set in soc_pre_ram_init when VBOOT_STARTS_IN_ROMSTAGE?
No.
...
Any suggestions for better solution?
Try https://review.coreboot.org/c/coreboot/+/52157 ?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Icfedfa82e746626f35e6f1d426a4de768c594b93
Gerrit-Change-Number: 52128
Gerrit-PatchSet: 7
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